[llvm] r356309 - [GlobalISel] Make isel verification checks of vregs run under NDEBUG only.
Amara Emerson via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 15 18:02:11 PDT 2019
Author: aemerson
Date: Fri Mar 15 18:02:10 2019
New Revision: 356309
URL: http://llvm.org/viewvc/llvm-project?rev=356309&view=rev
Log:
[GlobalISel] Make isel verification checks of vregs run under NDEBUG only.
Modified:
llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelect.cpp
Modified: llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelect.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelect.cpp?rev=356309&r1=356308&r2=356309&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelect.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelect.cpp Fri Mar 15 18:02:10 2019
@@ -89,10 +89,10 @@ bool InstructionSelect::runOnMachineFunc
"instruction is not legal", *MI);
return false;
}
-#endif
// FIXME: We could introduce new blocks and will need to fix the outer loop.
// Until then, keep track of the number of blocks to assert that we don't.
const size_t NumBlocks = MF.size();
+#endif
for (MachineBasicBlock *MBB : post_order(&MF)) {
if (MBB->empty())
@@ -144,8 +144,6 @@ bool InstructionSelect::runOnMachineFunc
}
}
- const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
-
for (MachineBasicBlock &MBB : MF) {
if (MBB.empty())
continue;
@@ -177,6 +175,8 @@ bool InstructionSelect::runOnMachineFunc
}
}
+#ifndef NDEBUG
+ const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
// Now that selection is complete, there are no more generic vregs. Verify
// that the size of the now-constrained vreg is unchanged and that it has a
// register class.
@@ -215,7 +215,7 @@ bool InstructionSelect::runOnMachineFunc
reportGISelFailure(MF, TPC, MORE, R);
return false;
}
-
+#endif
auto &TLI = *MF.getSubtarget().getTargetLowering();
TLI.finalizeLowering(MF);
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