[PATCH] D59383: [ARM] Add MachineVerifier logic for some Thumb1 instructions.
Eli Friedman via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 15 14:44:00 PDT 2019
This revision was automatically updated to reflect the committed changes.
Closed by commit rL356303: [ARM] Add MachineVerifier logic for some Thumb1 instructions. (authored by efriedma, committed by ).
Changed prior to commit:
https://reviews.llvm.org/D59383?vs=190704&id=190906#toc
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D59383/new/
https://reviews.llvm.org/D59383
Files:
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/trunk/test/CodeGen/ARM/machine-verifier.mir
Index: llvm/trunk/test/CodeGen/ARM/machine-verifier.mir
===================================================================
--- llvm/trunk/test/CodeGen/ARM/machine-verifier.mir
+++ llvm/trunk/test/CodeGen/ARM/machine-verifier.mir
@@ -0,0 +1,22 @@
+# RUN: not llc -mtriple=thumb -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# This test ensures that the MIR parser runs the machine verifier after parsing.
+
+--- |
+
+ define i32 @inc(i32 %a) {
+ entry:
+ ret i32 %a
+ }
+
+...
+---
+name: inc
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ ; CHECK: *** Bad machine code: Unsupported register in Thumb1 push/pop ***
+ frame-setup tPUSH 14, $noreg, undef $r12, killed $lr, implicit-def $sp, implicit $sp
+
+ ; CHECK: *** Bad machine code: Non-flag-setting Thumb1 mov is v6-only ***
+ $r2 = tMOVr killed $r6, 14, $noreg
+...
Index: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -4570,6 +4570,31 @@
ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
return false;
}
+ if (MI.getOpcode() == ARM::tMOVr && !Subtarget.hasV6Ops()) {
+ // Make sure we don't generate a lo-lo mov that isn't supported.
+ if (!ARM::hGPRRegClass.contains(MI.getOperand(0).getReg()) &&
+ !ARM::hGPRRegClass.contains(MI.getOperand(1).getReg())) {
+ ErrInfo = "Non-flag-setting Thumb1 mov is v6-only";
+ return false;
+ }
+ }
+ if (MI.getOpcode() == ARM::tPUSH ||
+ MI.getOpcode() == ARM::tPOP ||
+ MI.getOpcode() == ARM::tPOP_RET) {
+ for (int i = 2, e = MI.getNumOperands(); i < e; ++i) {
+ if (MI.getOperand(i).isImplicit() ||
+ !MI.getOperand(i).isReg())
+ continue;
+ unsigned Reg = MI.getOperand(i).getReg();
+ if (Reg < ARM::R0 || Reg > ARM::R7) {
+ if (!(MI.getOpcode() == ARM::tPUSH && Reg == ARM::LR) &&
+ !(MI.getOpcode() == ARM::tPOP_RET && Reg == ARM::PC)) {
+ ErrInfo = "Unsupported register in Thumb1 push/pop";
+ return false;
+ }
+ }
+ }
+ }
return true;
}
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