[llvm] r356182 - [GlobalISel][AArch64] Add partial selection support for G_INSERT_VECTOR_ELT
Jessica Paquette via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 15 12:52:18 PDT 2019
I think this should have been resolved in r356282.
- Jessica
> On Mar 15, 2019, at 12:35 PM, Adhemerval Zanella <adhemerval.zanella at linaro.org> wrote:
>
> This is causing a regression in aarch64 buildbots [1] on test-suite
> SingleSource/UnitTests/Vector/AArch64/aarch64_neon_intrinsics.c. The
> failure output shows:
>
> ---
> Starting tests now
> ReproInfo2 {semantics = "qrshr", fnname = "vqrshruns_n_s32", rettype = "uint16_t", argtypes = "[int32_t,__constrange(1,16) int]", vals = [IntegerVal 18580,IndexVal 4], start_saturated = False}
> Got unexpected saturation
> ReproInfo2 {semantics = "qshr", fnname = "vqshrns_n_u32", rettype = "uint16_t", argtypes = "[uint32_t,__constrange(1,16) int]", vals = [IntegerVal 0,IndexVal 11], start_saturated = False}
> Got unexpected saturation
> Test result: FAILED
> ---
>
> A reduced testcase from test-suite one that fails with master:
>
> ---
> #include <inttypes.h>
> #include <stdio.h>
> #include <arm_neon.h>
> #include <assert.h>
>
> static inline uint64_t get_fpsr()
> {
> uint64_t fpsr;
> __asm__ __volatile__ ("mrs %0, FPSR" : "=r"(fpsr) : : "memory");
> return fpsr;
> }
> static inline void set_fpsr(uint64_t mask, uint64_t value)
> {
> uint64_t fpsr=get_fpsr();
> fpsr = (fpsr & ~mask) | (value & mask);
> __asm__ __volatile__ ("msr FPSR, %0" : : "r"(fpsr) : "memory");
> }
> static __attribute__ ((noinline))
> void clear_neon_saturated(void)
> {
> set_fpsr(1<<27, 0);
> }
> static __attribute__ ((noinline))
> int get_neon_saturated(void)
> {
> return get_fpsr() & (1<<27) ? 1 : 0;
> }
>
> int main ()
> {
> clear_neon_saturated();
> // expect: "result" = 0489
> int32_t arg1 = 18580;
> uint16_t result = vqrshruns_n_s32(arg1, 4);
> assert (get_neon_saturated() == 0);
>
> uint16_t got = result;
> uint16_t exp = 1161u;
> assert (got == exp);
> return 0;
> }
> ---
>
> [1] http://lab.llvm.org:8011/builders/clang-cmake-aarch64-lld/builds/6231
>
> On 14/03/2019 15:01, Jessica Paquette via llvm-commits wrote:
>> Author: paquette
>> Date: Thu Mar 14 11:01:30 2019
>> New Revision: 356182
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=356182&view=rev
>> Log:
>> [GlobalISel][AArch64] Add partial selection support for G_INSERT_VECTOR_ELT
>>
>> This adds support for inserting elements into packed vectors. It also adds
>> two tests: one for selection, and one for regbank select.
>>
>> Unpacked vectors will come in a follow-up.
>>
>> Differential Revision: https://reviews.llvm.org/D59325
>>
>> Added:
>> llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir
>> llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
>> Modified:
>> llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
>> llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
>> llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
>> llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=356182&r1=356181&r2=356182&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
>> +++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Thu Mar 14 11:01:30 2019
>> @@ -82,6 +82,7 @@ private:
>> unsigned EltReg, unsigned LaneIdx,
>> const RegisterBank &RB,
>> MachineIRBuilder &MIRBuilder) const;
>> + bool selectInsertElt(MachineInstr &I, MachineRegisterInfo &MRI) const;
>> bool selectBuildVector(MachineInstr &I, MachineRegisterInfo &MRI) const;
>> bool selectMergeValues(MachineInstr &I, MachineRegisterInfo &MRI) const;
>> bool selectUnmergeValues(MachineInstr &I, MachineRegisterInfo &MRI) const;
>> @@ -1723,6 +1724,8 @@ bool AArch64InstructionSelector::select(
>> return selectShuffleVector(I, MRI);
>> case TargetOpcode::G_EXTRACT_VECTOR_ELT:
>> return selectExtractElt(I, MRI);
>> + case TargetOpcode::G_INSERT_VECTOR_ELT:
>> + return selectInsertElt(I, MRI);
>> }
>>
>> return false;
>> @@ -2346,6 +2349,42 @@ MachineInstr *AArch64InstructionSelector
>> return InsElt;
>> }
>>
>> +bool AArch64InstructionSelector::selectInsertElt(
>> + MachineInstr &I, MachineRegisterInfo &MRI) const {
>> + assert(I.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT);
>> +
>> + // Get information on the destination.
>> + unsigned DstReg = I.getOperand(0).getReg();
>> + const LLT DstTy = MRI.getType(DstReg);
>> + if (DstTy.getSizeInBits() < 128) {
>> + // TODO: Handle unpacked vectors.
>> + LLVM_DEBUG(dbgs() << "Unpacked vectors not supported yet!");
>> + return false;
>> + }
>> +
>> + // Get information on the element we want to insert into the destination.
>> + unsigned EltReg = I.getOperand(2).getReg();
>> + const LLT EltTy = MRI.getType(EltReg);
>> + unsigned EltSize = EltTy.getSizeInBits();
>> + if (EltSize < 16 || EltSize > 64)
>> + return false; // Don't support all element types yet.
>> +
>> + // Find the definition of the index. Bail out if it's not defined by a
>> + // G_CONSTANT.
>> + unsigned IdxReg = I.getOperand(3).getReg();
>> + unsigned LaneIdx = 0;
>> + if (!getConstantValueForReg(IdxReg, MRI, LaneIdx))
>> + return false;
>> +
>> + // Perform the lane insert.
>> + unsigned SrcReg = I.getOperand(1).getReg();
>> + const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI);
>> + MachineIRBuilder MIRBuilder(I);
>> + emitLaneInsert(DstReg, SrcReg, EltReg, LaneIdx, EltRB, MIRBuilder);
>> + I.eraseFromParent();
>> + return true;
>> +}
>> +
>> bool AArch64InstructionSelector::selectBuildVector(
>> MachineInstr &I, MachineRegisterInfo &MRI) const {
>> assert(I.getOpcode() == TargetOpcode::G_BUILD_VECTOR);
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=356182&r1=356181&r2=356182&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp Thu Mar 14 11:01:30 2019
>> @@ -450,6 +450,14 @@ AArch64LegalizerInfo::AArch64LegalizerIn
>> VecTy == v2s64 || VecTy == v2s32;
>> });
>>
>> + getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
>> + .legalIf([=](const LegalityQuery &Query) {
>> + const LLT &VecTy = Query.Types[0];
>> + // TODO: Support destination sizes of < 128 bits.
>> + // TODO: Support s8 and s16
>> + return VecTy == v4s32 || VecTy == v2s64;
>> + });
>> +
>> getActionDefinitionsBuilder(G_BUILD_VECTOR)
>> .legalFor({{v4s16, s16},
>> {v8s16, s16},
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=356182&r1=356181&r2=356182&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Thu Mar 14 11:01:30 2019
>> @@ -697,7 +697,19 @@ AArch64RegisterBankInfo::getInstrMapping
>> // Index needs to be a GPR.
>> OpRegBankIdx[2] = PMI_FirstGPR;
>> break;
>> + case TargetOpcode::G_INSERT_VECTOR_ELT:
>> + OpRegBankIdx[0] = PMI_FirstFPR;
>> + OpRegBankIdx[1] = PMI_FirstFPR;
>>
>> + // The element may be either a GPR or FPR. Preserve that behaviour.
>> + if (getRegBank(MI.getOperand(2).getReg(), MRI, TRI) == &AArch64::FPRRegBank)
>> + OpRegBankIdx[2] = PMI_FirstFPR;
>> + else
>> + OpRegBankIdx[2] = PMI_FirstGPR;
>> +
>> + // Index needs to be a GPR.
>> + OpRegBankIdx[3] = PMI_FirstGPR;
>> + break;
>> case TargetOpcode::G_BUILD_VECTOR:
>> // If the first source operand belongs to a FPR register bank, then make
>> // sure that we preserve that.
>>
>> Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir?rev=356182&r1=356181&r2=356182&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir (original)
>> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir Thu Mar 14 11:01:30 2019
>> @@ -307,7 +307,7 @@
>> # DEBUG: .. type index coverage check SKIPPED: no rules defined
>> #
>> # DEBUG-NEXT: G_INSERT_VECTOR_ELT (opcode {{[0-9]+}}): 3 type indices
>> -# DEBUG: .. type index coverage check SKIPPED: no rules defined
>> +# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
>> #
>> # DEBUG-NEXT: G_EXTRACT_VECTOR_ELT (opcode {{[0-9]+}}): 3 type indices
>> # DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
>>
>> Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir?rev=356182&view=auto
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir (added)
>> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir Thu Mar 14 11:01:30 2019
>> @@ -0,0 +1,113 @@
>> +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
>> +# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect %s -o - | FileCheck %s
>> +
>> +# The following should hold here:
>> +#
>> +# 1) The first and second operands of G_INSERT_VECTOR_ELT should be FPRs since
>> +# they are vectors.
>> +#
>> +# 2) The third operand should be on the register bank given in the test name
>> +# (e.g, v4s32_fpr). AArch64 supports native inserts of GPRs, so we need to
>> +# preserve that.
>> +#
>> +# 3) The fourth operand should be a GPR, since it's a constant.
>> +
>> +name: v4s32_fpr
>> +alignment: 2
>> +legalized: true
>> +tracksRegLiveness: true
>> +body: |
>> + bb.0:
>> + liveins: $q1, $s0
>> +
>> + ; CHECK-LABEL: name: v4s32_fpr
>> + ; CHECK: liveins: $q1, $s0
>> + ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
>> + ; CHECK: [[COPY1:%[0-9]+]]:fpr(<4 x s32>) = COPY $q1
>> + ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
>> + ; CHECK: [[IVEC:%[0-9]+]]:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32)
>> + ; CHECK: $q0 = COPY [[IVEC]](<4 x s32>)
>> + ; CHECK: RET_ReallyLR implicit $q0
>> + %0:_(s32) = COPY $s0
>> + %1:_(<4 x s32>) = COPY $q1
>> + %3:_(s32) = G_CONSTANT i32 1
>> + %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
>> + $q0 = COPY %2(<4 x s32>)
>> + RET_ReallyLR implicit $q0
>> +
>> +...
>> +---
>> +name: v4s32_gpr
>> +alignment: 2
>> +legalized: true
>> +tracksRegLiveness: true
>> +body: |
>> + bb.0:
>> + liveins: $q0, $w0
>> +
>> + ; CHECK-LABEL: name: v4s32_gpr
>> + ; CHECK: liveins: $q0, $w0
>> + ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
>> + ; CHECK: [[COPY1:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
>> + ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
>> + ; CHECK: [[IVEC:%[0-9]+]]:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32)
>> + ; CHECK: $q0 = COPY [[IVEC]](<4 x s32>)
>> + ; CHECK: RET_ReallyLR implicit $q0
>> + %0:_(s32) = COPY $w0
>> + %1:_(<4 x s32>) = COPY $q0
>> + %3:_(s32) = G_CONSTANT i32 1
>> + %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
>> + $q0 = COPY %2(<4 x s32>)
>> + RET_ReallyLR implicit $q0
>> +
>> +...
>> +---
>> +name: v2s64_fpr
>> +alignment: 2
>> +legalized: true
>> +tracksRegLiveness: true
>> +body: |
>> + bb.0:
>> + liveins: $d0, $q1
>> +
>> + ; CHECK-LABEL: name: v2s64_fpr
>> + ; CHECK: liveins: $d0, $q1
>> + ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
>> + ; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s64>) = COPY $q1
>> + ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1
>> + ; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s64), [[C]](s32)
>> + ; CHECK: $q0 = COPY [[IVEC]](<2 x s64>)
>> + ; CHECK: RET_ReallyLR implicit $q0
>> + %0:_(s64) = COPY $d0
>> + %1:_(<2 x s64>) = COPY $q1
>> + %3:_(s32) = G_CONSTANT i32 1
>> + %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32)
>> + $q0 = COPY %2(<2 x s64>)
>> + RET_ReallyLR implicit $q0
>> +
>> +...
>> +---
>> +name: v2s64_gpr
>> +alignment: 2
>> +legalized: true
>> +tracksRegLiveness: true
>> +body: |
>> + bb.0:
>> + liveins: $q0, $x0
>> +
>> + ; CHECK-LABEL: name: v2s64_gpr
>> + ; CHECK: liveins: $q0, $x0
>> + ; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0
>> + ; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0
>> + ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
>> + ; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s64), [[C]](s32)
>> + ; CHECK: $q0 = COPY [[IVEC]](<2 x s64>)
>> + ; CHECK: RET_ReallyLR implicit $q0
>> + %0:_(s64) = COPY $x0
>> + %1:_(<2 x s64>) = COPY $q0
>> + %3:_(s32) = G_CONSTANT i32 0
>> + %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32)
>> + $q0 = COPY %2(<2 x s64>)
>> + RET_ReallyLR implicit $q0
>> +
>> +...
>>
>> Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir?rev=356182&view=auto
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir (added)
>> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir Thu Mar 14 11:01:30 2019
>> @@ -0,0 +1,106 @@
>> +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
>> +# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select %s -o - | FileCheck %s
>> +
>> +name: v4s32_fpr
>> +alignment: 2
>> +legalized: true
>> +regBankSelected: true
>> +tracksRegLiveness: true
>> +body: |
>> + bb.0:
>> + liveins: $q1, $s0
>> +
>> + ; CHECK-LABEL: name: v4s32_fpr
>> + ; CHECK: liveins: $q1, $s0
>> + ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
>> + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
>> + ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
>> + ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub
>> + ; CHECK: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
>> + ; CHECK: $q0 = COPY [[INSvi32lane]]
>> + ; CHECK: RET_ReallyLR implicit $q0
>> + %0:fpr(s32) = COPY $s0
>> + %1:fpr(<4 x s32>) = COPY $q1
>> + %3:gpr(s32) = G_CONSTANT i32 1
>> + %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
>> + $q0 = COPY %2(<4 x s32>)
>> + RET_ReallyLR implicit $q0
>> +
>> +...
>> +---
>> +name: v4s32_gpr
>> +alignment: 2
>> +legalized: true
>> +regBankSelected: true
>> +tracksRegLiveness: true
>> +body: |
>> + bb.0:
>> + liveins: $q0, $w0
>> +
>> + ; CHECK-LABEL: name: v4s32_gpr
>> + ; CHECK: liveins: $q0, $w0
>> + ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
>> + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
>> + ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[COPY1]], 1, [[COPY]]
>> + ; CHECK: $q0 = COPY [[INSvi32gpr]]
>> + ; CHECK: RET_ReallyLR implicit $q0
>> + %0:gpr(s32) = COPY $w0
>> + %1:fpr(<4 x s32>) = COPY $q0
>> + %3:gpr(s32) = G_CONSTANT i32 1
>> + %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
>> + $q0 = COPY %2(<4 x s32>)
>> + RET_ReallyLR implicit $q0
>> +
>> +...
>> +---
>> +name: v2s64_fpr
>> +alignment: 2
>> +legalized: true
>> +regBankSelected: true
>> +tracksRegLiveness: true
>> +body: |
>> + bb.0:
>> + liveins: $d0, $q1
>> +
>> + ; CHECK-LABEL: name: v2s64_fpr
>> + ; CHECK: liveins: $d0, $q1
>> + ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
>> + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
>> + ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
>> + ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
>> + ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
>> + ; CHECK: $q0 = COPY [[INSvi64lane]]
>> + ; CHECK: RET_ReallyLR implicit $q0
>> + %0:fpr(s64) = COPY $d0
>> + %1:fpr(<2 x s64>) = COPY $q1
>> + %3:gpr(s32) = G_CONSTANT i32 1
>> + %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32)
>> + $q0 = COPY %2(<2 x s64>)
>> + RET_ReallyLR implicit $q0
>> +
>> +...
>> +---
>> +name: v2s64_gpr
>> +alignment: 2
>> +legalized: true
>> +regBankSelected: true
>> +tracksRegLiveness: true
>> +body: |
>> + bb.0:
>> + liveins: $q0, $x0
>> +
>> + ; CHECK-LABEL: name: v2s64_gpr
>> + ; CHECK: liveins: $q0, $x0
>> + ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
>> + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
>> + ; CHECK: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[COPY1]], 0, [[COPY]]
>> + ; CHECK: $q0 = COPY [[INSvi64gpr]]
>> + ; CHECK: RET_ReallyLR implicit $q0
>> + %0:gpr(s64) = COPY $x0
>> + %1:fpr(<2 x s64>) = COPY $q0
>> + %3:gpr(s32) = G_CONSTANT i32 0
>> + %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32)
>> + $q0 = COPY %2(<2 x s64>)
>> + RET_ReallyLR implicit $q0
>> +
>> +...
>>
>>
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