[PATCH] D59410: [ARM] Remove EarlyCSE from backend

[Sam Parker via Phabricator via llvm-commits]

samparker created this revision.
samparker added a reviewer: mstorsjo.
Herald added subscribers: zzheng, kristof.beyls, javed.absar.

There is an issue with early CSE hitting an assert, so temporarily remove the pass from the Arm backend.
Bug: https://bugs.llvm.org/show_bug.cgi?id=41081


https://reviews.llvm.org/D59410

Files:
  lib/Target/ARM/ARMTargetMachine.cpp
  test/CodeGen/ARM/O3-pipeline.ll
  test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
  test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll


Index: test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
===================================================================
--- test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
+++ test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
@@ -32,12 +32,13 @@
 
 define fastcc i32 @parse_percent_token() nounwind {
 entry:
-; CHECK: bx lr
-; CHECK: bx lr
-; CHECK: bx lr
-; CHECK: bx lr
-; CHECK: bx lr
-; CHECK: bx lr
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
 ; Do not convert into single stream code. BranchProbability Analysis assumes
 ; that branches which goes to "ret" instruction have lower probabilities.
   switch i32 undef, label %bb7 [
Index: test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
===================================================================
--- test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
+++ test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
@@ -31,15 +31,11 @@
   %inc11.us.i.3.i = add i32 %idx, 4
   br label %for.body
 
+; TODO: CSE, or something similar, is required to remove the duplicate loads.
 ; CHECK: %for.body
 ; CHECK: smlad
 ; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
+; CHECK-NOT: smlad r{{.*}}
 
 for.body:
   %A3 = phi i32 [ %add9.us.i.3361.i, %for.body ], [ 0, %entry ]
Index: test/CodeGen/ARM/O3-pipeline.ll
===================================================================
--- test/CodeGen/ARM/O3-pipeline.ll
+++ test/CodeGen/ARM/O3-pipeline.ll
@@ -33,7 +33,6 @@
 ; CHECK:      Scalarize Masked Memory Intrinsics
 ; CHECK:      Expand reduction intrinsics
 ; CHECK:      Dominator Tree Construction
-; CHECK:      Early CSE
 ; CHECK:      Natural Loop Information
 ; CHECK:      Scalar Evolution Analysis
 ; CHECK:      Basic Alias Analysis (stateless AA impl)
Index: lib/Target/ARM/ARMTargetMachine.cpp
===================================================================
--- lib/Target/ARM/ARMTargetMachine.cpp
+++ lib/Target/ARM/ARMTargetMachine.cpp
@@ -403,11 +403,9 @@
 
   TargetPassConfig::addIRPasses();
 
-  // Run the parallel DSP pass and its helpers.
-  if (getOptLevel() == CodeGenOpt::Aggressive) {
-    addPass(createEarlyCSEPass());
+  // Run the parallel DSP pass.
+  if (getOptLevel() == CodeGenOpt::Aggressive) 
     addPass(createARMParallelDSPPass());
-  }
 
   // Match interleaved memory accesses to ldN/stN intrinsics.
   if (TM->getOptLevel() != CodeGenOpt::None)


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