[llvm] r356238 - [MIPS GlobalISel] Improve selection of constants
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 15 00:07:50 PDT 2019
Author: petar.avramovic
Date: Fri Mar 15 00:07:50 2019
New Revision: 356238
URL: http://llvm.org/viewvc/llvm-project?rev=356238&view=rev
Log:
[MIPS GlobalISel] Improve selection of constants
Certain 32 bit constants can be generated with a single instruction
instead of two. Implement materialize32BitImm function for MIPS32.
Differential Revision: https://reviews.llvm.org/D59369
Added:
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/constants.mir
Modified:
llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/stack_args.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll
Modified: llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp Fri Mar 15 00:07:50 2019
@@ -36,6 +36,8 @@ public:
private:
bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
+ bool materialize32BitImm(unsigned DestReg, APInt Imm,
+ MachineIRBuilder &B) const;
const MipsTargetMachine &TM;
const MipsSubtarget &STI;
@@ -90,6 +92,40 @@ static bool selectCopy(MachineInstr &I,
return true;
}
+bool MipsInstructionSelector::materialize32BitImm(unsigned DestReg, APInt Imm,
+ MachineIRBuilder &B) const {
+ assert(Imm.getBitWidth() == 32 && "Unsupported immediate size.");
+ // Ori zero extends immediate. Used for values with zeros in high 16 bits.
+ if (Imm.getHiBits(16).isNullValue()) {
+ MachineInstr *Inst = B.buildInstr(Mips::ORi, {DestReg}, {Mips::ZERO})
+ .addImm(Imm.getLoBits(16).getLimitedValue());
+ return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
+ }
+ // Lui places immediate in high 16 bits and sets low 16 bits to zero.
+ if (Imm.getLoBits(16).isNullValue()) {
+ MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {})
+ .addImm(Imm.getHiBits(16).getLimitedValue());
+ return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
+ }
+ // ADDiu sign extends immediate. Used for values with 1s in high 17 bits.
+ if (Imm.isSignedIntN(16)) {
+ MachineInstr *Inst = B.buildInstr(Mips::ADDiu, {DestReg}, {Mips::ZERO})
+ .addImm(Imm.getLoBits(16).getLimitedValue());
+ return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
+ }
+ // Values that cannot be materialized with single immediate instruction.
+ unsigned LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass);
+ MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {})
+ .addImm(Imm.getHiBits(16).getLimitedValue());
+ MachineInstr *ORi = B.buildInstr(Mips::ORi, {DestReg}, {LUiReg})
+ .addImm(Imm.getLoBits(16).getLimitedValue());
+ if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
+ return false;
+ if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI))
+ return false;
+ return true;
+}
+
/// Returning Opc indicates that we failed to select MIPS instruction opcode.
static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned MemSizeInBytes) {
if (Opc == TargetOpcode::G_STORE)
@@ -266,22 +302,9 @@ bool MipsInstructionSelector::select(Mac
break;
}
case G_CONSTANT: {
- int Imm = I.getOperand(1).getCImm()->getValue().getLimitedValue();
- unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
- MachineInstr *LUi, *ORi;
-
- LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
- .addDef(LUiReg)
- .addImm(Imm >> 16);
-
- ORi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ORi))
- .addDef(I.getOperand(0).getReg())
- .addUse(LUiReg)
- .addImm(Imm & 0xFFFF);
-
- if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
- return false;
- if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI))
+ MachineIRBuilder B(I);
+ if (!materialize32BitImm(I.getOperand(0).getReg(),
+ I.getOperand(1).getCImm()->getValue(), B))
return false;
I.eraseFromParent();
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir Fri Mar 15 00:07:50 2019
@@ -71,8 +71,7 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
- ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
; MIPS32: BNE [[AND]], $zero, %bb.1, implicit-def $at
; MIPS32: J %bb.2, implicit-def $at
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/constants.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/constants.mir?rev=356238&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/constants.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/constants.mir Fri Mar 15 00:07:50 2019
@@ -0,0 +1,80 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+ define void @_0xABCD0000() {entry: ret void}
+ define void @_0x00008000() {entry: ret void}
+ define void @_0xFFFFFFF6() {entry: ret void}
+ define void @_0x0A0B0C0D() {entry: ret void}
+
+...
+---
+name: _0xABCD0000
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ ; MIPS32-LABEL: name: _0xABCD0000
+ ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 43981
+ ; MIPS32: $v0 = COPY [[LUi]]
+ ; MIPS32: RetRA implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1412628480
+ $v0 = COPY %0(s32)
+ RetRA implicit $v0
+
+...
+---
+name: _0x00008000
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ ; MIPS32-LABEL: name: _0x00008000
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 32768
+ ; MIPS32: $v0 = COPY [[ORi]]
+ ; MIPS32: RetRA implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 32768
+ $v0 = COPY %0(s32)
+ RetRA implicit $v0
+
+...
+---
+name: _0xFFFFFFF6
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ ; MIPS32-LABEL: name: _0xFFFFFFF6
+ ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65526
+ ; MIPS32: $v0 = COPY [[ADDiu]]
+ ; MIPS32: RetRA implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -10
+ $v0 = COPY %0(s32)
+ RetRA implicit $v0
+
+...
+---
+name: _0x0A0B0C0D
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ ; MIPS32-LABEL: name: _0x0A0B0C0D
+ ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 2571
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 3085
+ ; MIPS32: $v0 = COPY [[ORi]]
+ ; MIPS32: RetRA implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 168496141
+ $v0 = COPY %0(s32)
+ RetRA implicit $v0
+
+...
+
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir Fri Mar 15 00:07:50 2019
@@ -21,8 +21,7 @@ body: |
; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @.str
; MIPS32: [[LUi1:%[0-9]+]]:gpr32 = LUi 18838
; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi1]], 722
- ; MIPS32: [[LUi2:%[0-9]+]]:gpr32 = LUi 0
- ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi [[LUi2]], 0
+ ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 0
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[ADDiu]]
; MIPS32: $a1 = COPY [[ORi]]
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir Fri Mar 15 00:07:50 2019
@@ -30,8 +30,7 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
; MIPS32: [[SLTiu:%[0-9]+]]:gpr32 = SLTiu [[XOR]], 1
- ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTiu]], [[ORi]]
; MIPS32: $v0 = COPY [[AND]]
; MIPS32: RetRA implicit $v0
@@ -61,8 +60,7 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[XOR]]
- ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi]]
; MIPS32: $v0 = COPY [[AND]]
; MIPS32: RetRA implicit $v0
@@ -91,8 +89,7 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY1]], [[COPY]]
- ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLT]], [[ORi]]
; MIPS32: $v0 = COPY [[AND]]
; MIPS32: RetRA implicit $v0
@@ -122,8 +119,7 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY]], [[COPY1]]
; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLT]], 1
- ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]]
; MIPS32: $v0 = COPY [[AND]]
; MIPS32: RetRA implicit $v0
@@ -152,8 +148,7 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY]], [[COPY1]]
- ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLT]], [[ORi]]
; MIPS32: $v0 = COPY [[AND]]
; MIPS32: RetRA implicit $v0
@@ -183,8 +178,7 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY1]], [[COPY]]
; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLT]], 1
- ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]]
; MIPS32: $v0 = COPY [[AND]]
; MIPS32: RetRA implicit $v0
@@ -213,8 +207,7 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY1]], [[COPY]]
- ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi]]
; MIPS32: $v0 = COPY [[AND]]
; MIPS32: RetRA implicit $v0
@@ -244,8 +237,7 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY]], [[COPY1]]
; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLTu]], 1
- ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]]
; MIPS32: $v0 = COPY [[AND]]
; MIPS32: RetRA implicit $v0
@@ -274,8 +266,7 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY]], [[COPY1]]
- ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi]]
; MIPS32: $v0 = COPY [[AND]]
; MIPS32: RetRA implicit $v0
@@ -305,8 +296,7 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY1]], [[COPY]]
; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLTu]], 1
- ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]]
; MIPS32: $v0 = COPY [[AND]]
; MIPS32: RetRA implicit $v0
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir Fri Mar 15 00:07:50 2019
@@ -49,12 +49,10 @@ body: |
; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def dead $hi0, implicit-def dead $lo0
; MIPS32: [[PseudoMULTu:%[0-9]+]]:acc64 = PseudoMULTu [[COPY]], [[COPY1]]
; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoMULTu]]
- ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 0
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[PseudoMFHI]], [[ORi]]
; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[XOR]]
- ; MIPS32: [[LUi1:%[0-9]+]]:gpr32 = LUi 0
- ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi [[LUi1]], 1
+ ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi1]]
; MIPS32: SB [[AND]], [[COPY3]], 0 :: (store 1 into %ir.pcarry_flag)
; MIPS32: SW [[MUL]], [[COPY2]], 0 :: (store 4 into %ir.pmul)
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir Fri Mar 15 00:07:50 2019
@@ -32,8 +32,7 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
- ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
; MIPS32: BNE [[AND]], $zero, %bb.1, implicit-def $at
; MIPS32: J %bb.2, implicit-def $at
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir Fri Mar 15 00:07:50 2019
@@ -21,8 +21,7 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
- ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
; MIPS32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
; MIPS32: $v0 = COPY [[MOVN_I_I]]
@@ -53,8 +52,7 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
- ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
; MIPS32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
; MIPS32: $v0 = COPY [[MOVN_I_I]]
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir Fri Mar 15 00:07:50 2019
@@ -32,8 +32,7 @@ body: |
; MIPS32: $a2 = COPY [[COPY2]]
; MIPS32: $a3 = COPY [[COPY3]]
; MIPS32: [[COPY4:%[0-9]+]]:gpr32 = COPY $sp
- ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
- ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 16
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[COPY4]], [[ORi]]
; MIPS32: SW [[LW]], [[ADDu]], 0 :: (store 4 into stack + 16)
; MIPS32: JAL @f, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll Fri Mar 15 00:07:50 2019
@@ -28,8 +28,7 @@ define zeroext i8 @add_i8_zext(i8 zeroex
; MIPS32-LABEL: add_i8_zext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addu $4, $5, $4
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 255
+; MIPS32-NEXT: ori $5, $zero, 255
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -66,8 +65,7 @@ define zeroext i16 @add_i16_zext(i16 zer
; MIPS32-LABEL: add_i16_zext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addu $4, $5, $4
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 65535
+; MIPS32-NEXT: ori $5, $zero, 65535
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -90,17 +88,14 @@ entry:
define i64 @add_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: add_i64:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, 0
-; MIPS32-NEXT: ori $1, $1, 0
+; MIPS32-NEXT: ori $1, $zero, 0
; MIPS32-NEXT: addu $4, $6, $4
-; MIPS32-NEXT: lui $2, 0
-; MIPS32-NEXT: ori $2, $2, 1
+; MIPS32-NEXT: ori $2, $zero, 1
; MIPS32-NEXT: and $1, $1, $2
; MIPS32-NEXT: addu $1, $4, $1
; MIPS32-NEXT: sltu $2, $1, $6
; MIPS32-NEXT: addu $4, $7, $5
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 1
+; MIPS32-NEXT: ori $5, $zero, 1
; MIPS32-NEXT: and $2, $2, $5
; MIPS32-NEXT: addu $3, $4, $2
; MIPS32-NEXT: move $2, $1
@@ -124,29 +119,24 @@ define i128 @add_i128(i128 %a, i128 %b)
; MIPS32-NEXT: lw $3, 0($3)
; MIPS32-NEXT: addiu $8, $sp, 36
; MIPS32-NEXT: lw $8, 0($8)
-; MIPS32-NEXT: lui $9, 0
-; MIPS32-NEXT: ori $9, $9, 0
+; MIPS32-NEXT: ori $9, $zero, 0
; MIPS32-NEXT: addu $4, $1, $4
-; MIPS32-NEXT: lui $10, 0
-; MIPS32-NEXT: ori $10, $10, 1
+; MIPS32-NEXT: ori $10, $zero, 1
; MIPS32-NEXT: and $9, $9, $10
; MIPS32-NEXT: addu $4, $4, $9
; MIPS32-NEXT: sltu $1, $4, $1
; MIPS32-NEXT: addu $5, $2, $5
-; MIPS32-NEXT: lui $9, 0
-; MIPS32-NEXT: ori $9, $9, 1
+; MIPS32-NEXT: ori $9, $zero, 1
; MIPS32-NEXT: and $1, $1, $9
; MIPS32-NEXT: addu $1, $5, $1
; MIPS32-NEXT: sltu $2, $1, $2
; MIPS32-NEXT: addu $5, $3, $6
-; MIPS32-NEXT: lui $6, 0
-; MIPS32-NEXT: ori $6, $6, 1
+; MIPS32-NEXT: ori $6, $zero, 1
; MIPS32-NEXT: and $2, $2, $6
; MIPS32-NEXT: addu $2, $5, $2
; MIPS32-NEXT: sltu $3, $2, $3
; MIPS32-NEXT: addu $5, $8, $7
-; MIPS32-NEXT: lui $6, 0
-; MIPS32-NEXT: ori $6, $6, 1
+; MIPS32-NEXT: ori $6, $zero, 1
; MIPS32-NEXT: and $3, $3, $6
; MIPS32-NEXT: addu $5, $5, $3
; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
@@ -167,8 +157,7 @@ define void @uadd_with_overflow(i32 %lhs
; MIPS32: # %bb.0:
; MIPS32-NEXT: addu $4, $4, $5
; MIPS32-NEXT: sltu $5, $4, $5
-; MIPS32-NEXT: lui $1, 0
-; MIPS32-NEXT: ori $1, $1, 1
+; MIPS32-NEXT: ori $1, $zero, 1
; MIPS32-NEXT: and $1, $5, $1
; MIPS32-NEXT: sb $1, 0($7)
; MIPS32-NEXT: sw $4, 0($6)
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll Fri Mar 15 00:07:50 2019
@@ -30,8 +30,7 @@ define i32 @Conditional_branch(i1 %cond,
; MIPS32: # %bb.0:
; MIPS32-NEXT: addiu $sp, $sp, -8
; MIPS32-NEXT: .cfi_def_cfa_offset 8
-; MIPS32-NEXT: lui $1, 0
-; MIPS32-NEXT: ori $1, $1, 1
+; MIPS32-NEXT: ori $1, $zero, 1
; MIPS32-NEXT: and $1, $4, $1
; MIPS32-NEXT: sw $5, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 0($sp) # 4-byte Folded Spill
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll Fri Mar 15 00:07:50 2019
@@ -4,10 +4,8 @@
define i64 @any_i64() {
; MIPS32-LABEL: any_i64:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, 0
-; MIPS32-NEXT: ori $2, $1, 0
-; MIPS32-NEXT: lui $1, 32768
-; MIPS32-NEXT: ori $3, $1, 0
+; MIPS32-NEXT: ori $2, $zero, 0
+; MIPS32-NEXT: lui $3, 32768
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -17,8 +15,7 @@ entry:
define i32 @any_i32() {
; MIPS32-LABEL: any_i32:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, 32768
-; MIPS32-NEXT: ori $2, $1, 0
+; MIPS32-NEXT: lui $2, 32768
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -28,8 +25,7 @@ entry:
define signext i16 @signed_i16() {
; MIPS32-LABEL: signed_i16:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, 65535
-; MIPS32-NEXT: ori $1, $1, 32768
+; MIPS32-NEXT: addiu $1, $zero, 32768
; MIPS32-NEXT: sll $1, $1, 16
; MIPS32-NEXT: sra $2, $1, 16
; MIPS32-NEXT: jr $ra
@@ -41,8 +37,7 @@ entry:
define signext i8 @signed_i8() {
; MIPS32-LABEL: signed_i8:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, 65535
-; MIPS32-NEXT: ori $1, $1, 65408
+; MIPS32-NEXT: addiu $1, $zero, 65408
; MIPS32-NEXT: sll $1, $1, 24
; MIPS32-NEXT: sra $2, $1, 24
; MIPS32-NEXT: jr $ra
@@ -54,10 +49,8 @@ entry:
define zeroext i16 @unsigned_i16() {
; MIPS32-LABEL: unsigned_i16:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, 65535
-; MIPS32-NEXT: ori $1, $1, 32768
-; MIPS32-NEXT: lui $2, 0
-; MIPS32-NEXT: ori $2, $2, 65535
+; MIPS32-NEXT: addiu $1, $zero, 32768
+; MIPS32-NEXT: ori $2, $zero, 65535
; MIPS32-NEXT: and $2, $1, $2
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -68,10 +61,8 @@ entry:
define zeroext i8 @unsigned_i8() {
; MIPS32-LABEL: unsigned_i8:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, 65535
-; MIPS32-NEXT: ori $1, $1, 65408
-; MIPS32-NEXT: lui $2, 0
-; MIPS32-NEXT: ori $2, $2, 255
+; MIPS32-NEXT: addiu $1, $zero, 65408
+; MIPS32-NEXT: ori $2, $zero, 255
; MIPS32-NEXT: and $2, $1, $2
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -82,10 +73,8 @@ entry:
define zeroext i1 @i1_true() {
; MIPS32-LABEL: i1_true:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, 65535
-; MIPS32-NEXT: ori $1, $1, 65535
-; MIPS32-NEXT: lui $2, 0
-; MIPS32-NEXT: ori $2, $2, 1
+; MIPS32-NEXT: addiu $1, $zero, 65535
+; MIPS32-NEXT: ori $2, $zero, 1
; MIPS32-NEXT: and $2, $1, $2
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -96,13 +85,52 @@ entry:
define zeroext i1 @i1_false() {
; MIPS32-LABEL: i1_false:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, 0
-; MIPS32-NEXT: ori $1, $1, 0
-; MIPS32-NEXT: lui $2, 0
-; MIPS32-NEXT: ori $2, $2, 1
+; MIPS32-NEXT: ori $1, $zero, 0
+; MIPS32-NEXT: ori $2, $zero, 1
; MIPS32-NEXT: and $2, $1, $2
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
ret i1 false
}
+
+define i32 @_0xABCD0000() {
+; MIPS32-LABEL: _0xABCD0000:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: lui $2, 43981
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ ret i32 -1412628480
+}
+
+define i32 @_0x00008000() {
+; MIPS32-LABEL: _0x00008000:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: ori $2, $zero, 32768
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ ret i32 32768
+}
+
+define i32 @_0xFFFFFFF6() {
+; MIPS32-LABEL: _0xFFFFFFF6:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: addiu $2, $zero, 65526
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ ret i32 -10
+}
+
+define i32 @_0x0A0B0C0D() {
+; MIPS32-LABEL: _0x0A0B0C0D:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: lui $1, 2571
+; MIPS32-NEXT: ori $2, $1, 3085
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ ret i32 168496141
+}
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address.ll?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address.ll Fri Mar 15 00:07:50 2019
@@ -14,8 +14,7 @@ define i32 @main() {
; MIPS32-NEXT: addiu $4, $1, %lo($.str)
; MIPS32-NEXT: lui $1, 18838
; MIPS32-NEXT: ori $5, $1, 722
-; MIPS32-NEXT: lui $1, 0
-; MIPS32-NEXT: ori $2, $1, 0
+; MIPS32-NEXT: ori $2, $zero, 0
; MIPS32-NEXT: sw $2, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: jal printf
; MIPS32-NEXT: nop
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll Fri Mar 15 00:07:50 2019
@@ -6,8 +6,7 @@ define i32 @eq(i32 %a, i32 %b){
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: xor $4, $4, $5
; MIPS32-NEXT: sltiu $4, $4, 1
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 1
+; MIPS32-NEXT: ori $5, $zero, 1
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -22,8 +21,7 @@ define i32 @ne(i32 %a, i32 %b) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: xor $4, $4, $5
; MIPS32-NEXT: sltu $4, $zero, $4
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 1
+; MIPS32-NEXT: ori $5, $zero, 1
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -37,8 +35,7 @@ define i32 @sgt(i32 %a, i32 %b) {
; MIPS32-LABEL: sgt:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: slt $4, $5, $4
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 1
+; MIPS32-NEXT: ori $5, $zero, 1
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -53,8 +50,7 @@ define i32 @sge(i32 %a, i32 %b) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: slt $4, $4, $5
; MIPS32-NEXT: xori $4, $4, 1
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 1
+; MIPS32-NEXT: ori $5, $zero, 1
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -68,8 +64,7 @@ define i32 @slt(i32 %a, i32 %b) {
; MIPS32-LABEL: slt:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: slt $4, $4, $5
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 1
+; MIPS32-NEXT: ori $5, $zero, 1
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -84,8 +79,7 @@ define i32 @sle(i32 %a, i32 %b) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: slt $4, $5, $4
; MIPS32-NEXT: xori $4, $4, 1
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 1
+; MIPS32-NEXT: ori $5, $zero, 1
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -99,8 +93,7 @@ define i32 @ugt(i32 %a, i32 %b) {
; MIPS32-LABEL: ugt:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sltu $4, $5, $4
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 1
+; MIPS32-NEXT: ori $5, $zero, 1
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -115,8 +108,7 @@ define i32 @uge(i32 %a, i32 %b) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sltu $4, $4, $5
; MIPS32-NEXT: xori $4, $4, 1
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 1
+; MIPS32-NEXT: ori $5, $zero, 1
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -130,8 +122,7 @@ define i32 @ult(i32 %a, i32 %b) {
; MIPS32-LABEL: ult:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sltu $4, $4, $5
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 1
+; MIPS32-NEXT: ori $5, $zero, 1
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -146,8 +137,7 @@ define i32 @ule(i32 %a, i32 %b) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sltu $4, $5, $4
; MIPS32-NEXT: xori $4, $4, 1
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 1
+; MIPS32-NEXT: ori $5, $zero, 1
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll Fri Mar 15 00:07:50 2019
@@ -28,8 +28,7 @@ define zeroext i8 @mul_i8_zext(i8 zeroex
; MIPS32-LABEL: mul_i8_zext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: mul $4, $5, $4
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 255
+; MIPS32-NEXT: ori $5, $zero, 255
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -66,8 +65,7 @@ define zeroext i16 @mul_i16_zext(i16 zer
; MIPS32-LABEL: mul_i16_zext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: mul $4, $5, $4
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 65535
+; MIPS32-NEXT: ori $5, $zero, 65535
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -122,13 +120,11 @@ define i128 @mul_i128(i128 %a, i128 %b)
; MIPS32-NEXT: mfhi $12
; MIPS32-NEXT: addu $10, $10, $11
; MIPS32-NEXT: sltu $11, $10, $11
-; MIPS32-NEXT: lui $13, 0
-; MIPS32-NEXT: ori $13, $13, 1
+; MIPS32-NEXT: ori $13, $zero, 1
; MIPS32-NEXT: and $11, $11, $13
; MIPS32-NEXT: addu $10, $10, $12
; MIPS32-NEXT: sltu $12, $10, $12
-; MIPS32-NEXT: lui $13, 0
-; MIPS32-NEXT: ori $13, $13, 1
+; MIPS32-NEXT: ori $13, $zero, 1
; MIPS32-NEXT: and $12, $12, $13
; MIPS32-NEXT: addu $11, $11, $12
; MIPS32-NEXT: mul $12, $3, $4
@@ -140,31 +136,26 @@ define i128 @mul_i128(i128 %a, i128 %b)
; MIPS32-NEXT: mfhi $24
; MIPS32-NEXT: addu $12, $12, $13
; MIPS32-NEXT: sltu $13, $12, $13
-; MIPS32-NEXT: lui $25, 0
-; MIPS32-NEXT: ori $25, $25, 1
+; MIPS32-NEXT: ori $25, $zero, 1
; MIPS32-NEXT: and $13, $13, $25
; MIPS32-NEXT: addu $12, $12, $14
; MIPS32-NEXT: sltu $14, $12, $14
-; MIPS32-NEXT: lui $25, 0
-; MIPS32-NEXT: ori $25, $25, 1
+; MIPS32-NEXT: ori $25, $zero, 1
; MIPS32-NEXT: and $14, $14, $25
; MIPS32-NEXT: addu $13, $13, $14
; MIPS32-NEXT: addu $12, $12, $15
; MIPS32-NEXT: sltu $14, $12, $15
-; MIPS32-NEXT: lui $15, 0
-; MIPS32-NEXT: ori $15, $15, 1
+; MIPS32-NEXT: ori $15, $zero, 1
; MIPS32-NEXT: and $14, $14, $15
; MIPS32-NEXT: addu $13, $13, $14
; MIPS32-NEXT: addu $12, $12, $24
; MIPS32-NEXT: sltu $14, $12, $24
-; MIPS32-NEXT: lui $15, 0
-; MIPS32-NEXT: ori $15, $15, 1
+; MIPS32-NEXT: ori $15, $zero, 1
; MIPS32-NEXT: and $14, $14, $15
; MIPS32-NEXT: addu $13, $13, $14
; MIPS32-NEXT: addu $12, $12, $11
; MIPS32-NEXT: sltu $11, $12, $11
-; MIPS32-NEXT: lui $14, 0
-; MIPS32-NEXT: ori $14, $14, 1
+; MIPS32-NEXT: ori $14, $zero, 1
; MIPS32-NEXT: and $11, $11, $14
; MIPS32-NEXT: addu $11, $13, $11
; MIPS32-NEXT: mul $8, $8, $4
@@ -201,12 +192,10 @@ define void @umul_with_overflow(i32 %lhs
; MIPS32-NEXT: mul $1, $4, $5
; MIPS32-NEXT: multu $4, $5
; MIPS32-NEXT: mfhi $4
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 0
+; MIPS32-NEXT: ori $5, $zero, 0
; MIPS32-NEXT: xor $4, $4, $5
; MIPS32-NEXT: sltu $4, $zero, $4
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 1
+; MIPS32-NEXT: ori $5, $zero, 1
; MIPS32-NEXT: and $4, $4, $5
; MIPS32-NEXT: sb $4, 0($7)
; MIPS32-NEXT: sw $1, 0($6)
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll Fri Mar 15 00:07:50 2019
@@ -6,8 +6,7 @@ define i1 @test_i1(i1 %cnd, i1 %a, i1 %b
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -16
; MIPS32-NEXT: .cfi_def_cfa_offset 16
-; MIPS32-NEXT: lui $1, 0
-; MIPS32-NEXT: ori $1, $1, 1
+; MIPS32-NEXT: ori $1, $zero, 1
; MIPS32-NEXT: and $1, $4, $1
; MIPS32-NEXT: sw $5, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 8($sp) # 4-byte Folded Spill
@@ -49,8 +48,7 @@ define i8 @test_i8(i1 %cnd, i8 %a, i8 %b
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -16
; MIPS32-NEXT: .cfi_def_cfa_offset 16
-; MIPS32-NEXT: lui $1, 0
-; MIPS32-NEXT: ori $1, $1, 1
+; MIPS32-NEXT: ori $1, $zero, 1
; MIPS32-NEXT: and $1, $4, $1
; MIPS32-NEXT: sw $5, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 8($sp) # 4-byte Folded Spill
@@ -92,8 +90,7 @@ define i16 @test_i16(i1 %cnd, i16 %a, i1
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -16
; MIPS32-NEXT: .cfi_def_cfa_offset 16
-; MIPS32-NEXT: lui $1, 0
-; MIPS32-NEXT: ori $1, $1, 1
+; MIPS32-NEXT: ori $1, $zero, 1
; MIPS32-NEXT: and $1, $4, $1
; MIPS32-NEXT: sw $5, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 8($sp) # 4-byte Folded Spill
@@ -135,8 +132,7 @@ define i32 @test_i32(i1 %cnd, i32 %a, i3
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -16
; MIPS32-NEXT: .cfi_def_cfa_offset 16
-; MIPS32-NEXT: lui $1, 0
-; MIPS32-NEXT: ori $1, $1, 1
+; MIPS32-NEXT: ori $1, $zero, 1
; MIPS32-NEXT: and $1, $4, $1
; MIPS32-NEXT: sw $5, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 8($sp) # 4-byte Folded Spill
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll Fri Mar 15 00:07:50 2019
@@ -157,11 +157,9 @@ entry:
define signext i8 @udiv_i8(i8 signext %a, i8 signext %b) {
; MIPS32-LABEL: udiv_i8:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, 0
-; MIPS32-NEXT: ori $1, $1, 255
+; MIPS32-NEXT: ori $1, $zero, 255
; MIPS32-NEXT: and $1, $5, $1
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 255
+; MIPS32-NEXT: ori $5, $zero, 255
; MIPS32-NEXT: and $4, $4, $5
; MIPS32-NEXT: divu $zero, $1, $4
; MIPS32-NEXT: teq $4, $zero, 7
@@ -178,11 +176,9 @@ entry:
define signext i16 @udiv_i16(i16 signext %a, i16 signext %b) {
; MIPS32-LABEL: udiv_i16:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, 0
-; MIPS32-NEXT: ori $1, $1, 65535
+; MIPS32-NEXT: ori $1, $zero, 65535
; MIPS32-NEXT: and $1, $5, $1
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 65535
+; MIPS32-NEXT: ori $5, $zero, 65535
; MIPS32-NEXT: and $4, $4, $5
; MIPS32-NEXT: divu $zero, $1, $4
; MIPS32-NEXT: teq $4, $zero, 7
@@ -237,11 +233,9 @@ entry:
define signext i8 @urem_i8(i8 signext %a, i8 signext %b) {
; MIPS32-LABEL: urem_i8:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, 0
-; MIPS32-NEXT: ori $1, $1, 255
+; MIPS32-NEXT: ori $1, $zero, 255
; MIPS32-NEXT: and $1, $5, $1
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 255
+; MIPS32-NEXT: ori $5, $zero, 255
; MIPS32-NEXT: and $4, $4, $5
; MIPS32-NEXT: divu $zero, $1, $4
; MIPS32-NEXT: teq $4, $zero, 7
@@ -258,11 +252,9 @@ entry:
define signext i16 @urem_i16(i16 signext %a, i16 signext %b) {
; MIPS32-LABEL: urem_i16:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, 0
-; MIPS32-NEXT: ori $1, $1, 65535
+; MIPS32-NEXT: ori $1, $zero, 65535
; MIPS32-NEXT: and $1, $5, $1
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 65535
+; MIPS32-NEXT: ori $5, $zero, 65535
; MIPS32-NEXT: and $4, $4, $5
; MIPS32-NEXT: divu $zero, $1, $4
; MIPS32-NEXT: teq $4, $zero, 7
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll Fri Mar 15 00:07:50 2019
@@ -4,8 +4,7 @@
define i8 @select_i8(i1 %test, i8 %a, i8 %b) {
; MIPS32-LABEL: select_i8:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, 0
-; MIPS32-NEXT: ori $1, $1, 1
+; MIPS32-NEXT: ori $1, $zero, 1
; MIPS32-NEXT: and $1, $4, $1
; MIPS32-NEXT: movn $6, $5, $1
; MIPS32-NEXT: move $2, $6
@@ -19,8 +18,7 @@ entry:
define i16 @select_i16(i1 %test, i16 %a, i16 %b) {
; MIPS32-LABEL: select_i16:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, 0
-; MIPS32-NEXT: ori $1, $1, 1
+; MIPS32-NEXT: ori $1, $zero, 1
; MIPS32-NEXT: and $1, $4, $1
; MIPS32-NEXT: movn $6, $5, $1
; MIPS32-NEXT: move $2, $6
@@ -34,8 +32,7 @@ entry:
define i32 @select_i32(i1 %test, i32 %a, i32 %b) {
; MIPS32-LABEL: select_i32:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, 0
-; MIPS32-NEXT: ori $1, $1, 1
+; MIPS32-NEXT: ori $1, $zero, 1
; MIPS32-NEXT: and $1, $4, $1
; MIPS32-NEXT: movn $6, $5, $1
; MIPS32-NEXT: move $2, $6
@@ -49,8 +46,7 @@ entry:
define i32* @select_ptr(i1 %test, i32* %a, i32* %b) {
; MIPS32-LABEL: select_ptr:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $1, 0
-; MIPS32-NEXT: ori $1, $1, 1
+; MIPS32-NEXT: ori $1, $zero, 1
; MIPS32-NEXT: and $1, $4, $1
; MIPS32-NEXT: movn $6, $5, $1
; MIPS32-NEXT: move $2, $6
@@ -66,8 +62,7 @@ define i32 @select_with_negation(i32 %a,
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: slt $4, $4, $5
; MIPS32-NEXT: not $4, $4
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 1
+; MIPS32-NEXT: ori $5, $zero, 1
; MIPS32-NEXT: and $4, $4, $5
; MIPS32-NEXT: movn $7, $6, $4
; MIPS32-NEXT: move $2, $7
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/stack_args.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/stack_args.ll?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/stack_args.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/stack_args.ll Fri Mar 15 00:07:50 2019
@@ -13,8 +13,7 @@ define i32 @g(i32 %x1, i32 %x2, i32 %x
; MIPS32-NEXT: addiu $1, $sp, 48
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: move $2, $sp
-; MIPS32-NEXT: lui $3, 0
-; MIPS32-NEXT: ori $3, $3, 16
+; MIPS32-NEXT: ori $3, $zero, 1
; MIPS32-NEXT: addu $2, $2, $3
; MIPS32-NEXT: sw $1, 0($2)
; MIPS32-NEXT: jal f
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll Fri Mar 15 00:07:50 2019
@@ -29,8 +29,7 @@ define zeroext i8 @sub_i8_zext(i8 zeroex
; MIPS32-LABEL: sub_i8_zext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: subu $4, $5, $4
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 255
+; MIPS32-NEXT: ori $5, $zero, 255
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -67,8 +66,7 @@ define zeroext i16 @sub_i16_zext(i16 zer
; MIPS32-LABEL: sub_i16_zext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: subu $4, $5, $4
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 65535
+; MIPS32-NEXT: ori $5, $zero, 65535
; MIPS32-NEXT: and $2, $4, $5
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -94,8 +92,7 @@ define i64 @sub_i64(i64 %a, i64 %b) {
; MIPS32-NEXT: subu $2, $6, $4
; MIPS32-NEXT: sltu $4, $6, $4
; MIPS32-NEXT: subu $5, $7, $5
-; MIPS32-NEXT: lui $6, 0
-; MIPS32-NEXT: ori $6, $6, 1
+; MIPS32-NEXT: ori $6, $zero, 1
; MIPS32-NEXT: and $4, $4, $6
; MIPS32-NEXT: subu $3, $5, $4
; MIPS32-NEXT: jr $ra
@@ -119,32 +116,27 @@ define i128 @sub_i128(i128 %a, i128 %b)
; MIPS32-NEXT: subu $9, $1, $4
; MIPS32-NEXT: sltu $1, $1, $4
; MIPS32-NEXT: subu $4, $2, $5
-; MIPS32-NEXT: lui $10, 0
-; MIPS32-NEXT: ori $10, $10, 1
+; MIPS32-NEXT: ori $10, $zero, 1
; MIPS32-NEXT: and $10, $1, $10
; MIPS32-NEXT: subu $4, $4, $10
; MIPS32-NEXT: xor $10, $2, $5
; MIPS32-NEXT: sltiu $10, $10, 1
; MIPS32-NEXT: sltu $2, $2, $5
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 1
+; MIPS32-NEXT: ori $5, $zero, 1
; MIPS32-NEXT: and $5, $10, $5
; MIPS32-NEXT: movn $2, $1, $5
; MIPS32-NEXT: subu $1, $3, $6
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 1
+; MIPS32-NEXT: ori $5, $zero, 1
; MIPS32-NEXT: and $5, $2, $5
; MIPS32-NEXT: subu $1, $1, $5
; MIPS32-NEXT: xor $5, $3, $6
; MIPS32-NEXT: sltiu $5, $5, 1
; MIPS32-NEXT: sltu $3, $3, $6
-; MIPS32-NEXT: lui $6, 0
-; MIPS32-NEXT: ori $6, $6, 1
+; MIPS32-NEXT: ori $6, $zero, 1
; MIPS32-NEXT: and $5, $5, $6
; MIPS32-NEXT: movn $3, $2, $5
; MIPS32-NEXT: subu $2, $8, $7
-; MIPS32-NEXT: lui $5, 0
-; MIPS32-NEXT: ori $5, $5, 1
+; MIPS32-NEXT: ori $5, $zero, 1
; MIPS32-NEXT: and $3, $3, $5
; MIPS32-NEXT: subu $5, $2, $3
; MIPS32-NEXT: move $2, $9
Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll?rev=356238&r1=356237&r2=356238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll Fri Mar 15 00:07:50 2019
@@ -27,8 +27,7 @@ define void @load_store_i1(i1* %px, i1*
; MIPS32-LABEL: load_store_i1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lbu $5, 0($5)
-; MIPS32-NEXT: lui $1, 0
-; MIPS32-NEXT: ori $1, $1, 1
+; MIPS32-NEXT: ori $1, $zero, 1
; MIPS32-NEXT: and $1, $5, $1
; MIPS32-NEXT: sb $1, 0($4)
; MIPS32-NEXT: jr $ra
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