[PATCH] D59362: [AMDGPU] Fix SGPR fixing through SCC chaining

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/udivrem64.ll:172-184
+;FUNC-LABEL: {{^}}test_udiv_k:
+;GCN: v_mul{{.+}} v{{[0-9]+}}, v{{[0-9]+}}, 24
+;GCN: v_mul{{.+}} v{{[0-9]+}}, v{{[0-9]+}}, 24
+;GCN: v_mul{{.+}} v{{[0-9]+}}, v{{[0-9]+}}, 24
+;GCN: v_add
+;GCN: v_addc
+;GCN: v_addc
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hliao wrote:
> arsenm wrote:
> > I don't see how this is stressing this. Can you add another, more targeted test for this? The div expansion is huge
> This is case where I found the long SCC chain(s). Yeah, the expansion is huge. But, to constructing a SCC chain with parts of instructions without SGPR dependency but SCC dependency is hard, also that sequence needs part of code has to use VGPR. Could you just use this minimalist LLVM IR test?
You can also use a MIR test


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D59362/new/

https://reviews.llvm.org/D59362