[llvm] r356122 - [RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegs
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 14 01:17:44 PDT 2019
Author: asb
Date: Thu Mar 14 01:17:44 2019
New Revision: 356122
URL: http://llvm.org/viewvc/llvm-project?rev=356122&view=rev
Log:
[RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegs
Add a caller which exhausts regs then calls another function. This allows
getCalleePreservedRegs to be tested.
Modified:
llvm/trunk/test/CodeGen/RISCV/callee-saved-fpr32s.ll
llvm/trunk/test/CodeGen/RISCV/callee-saved-fpr64s.ll
llvm/trunk/test/CodeGen/RISCV/callee-saved-gprs.ll
Modified: llvm/trunk/test/CodeGen/RISCV/callee-saved-fpr32s.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/callee-saved-fpr32s.ll?rev=356122&r1=356121&r2=356122&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/callee-saved-fpr32s.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/callee-saved-fpr32s.ll Thu Mar 14 01:17:44 2019
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=ILP32-LP64
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
@@ -8,8 +7,11 @@
; All floating point registers are temporaries for the ilp32 and lp64 ABIs.
-define void @foo() {
-; ILP32-LP64-LABEL: foo:
+; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns
+; something appropriate.
+
+define void @callee() {
+; ILP32-LP64-LABEL: callee:
; ILP32-LP64: # %bb.0:
; ILP32-LP64-NEXT: lui a0, %hi(var)
; ILP32-LP64-NEXT: addi a1, a0, %lo(var)
@@ -82,3 +84,24 @@ define void @foo() {
store volatile [32 x float] %val, [32 x float]* @var
ret void
}
+
+; This function tests that RISCVRegisterInfo::getCallPreservedMask returns
+; something appropriate.
+;
+; For the soft float ABIs, no floating point registers are preserved, and
+; codegen will use only ft0 in the body of caller.
+
+define void @caller() {
+; ILP32-LP64-LABEL: caller:
+; ILP32-LP64-NOT: ft{{[1-9][0-9]*}}
+; ILP32-LP64-NOT: fs{{[0-9]+}}
+; ILP32-LP64-NOT: fa{{[0-9]+}}
+; ILP32-LP64: ret
+; ILP32-LP64-NOT: ft{{[1-9][0-9]*}}
+; ILP32-LP64-NOT: fs{{[0-9]+}}
+; ILP32-LP64-NOT: fa{{[0-9]+}}
+ %val = load [32 x float], [32 x float]* @var
+ call void @callee()
+ store volatile [32 x float] %val, [32 x float]* @var
+ ret void
+}
Modified: llvm/trunk/test/CodeGen/RISCV/callee-saved-fpr64s.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/callee-saved-fpr64s.ll?rev=356122&r1=356121&r2=356122&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/callee-saved-fpr64s.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/callee-saved-fpr64s.ll Thu Mar 14 01:17:44 2019
@@ -8,8 +8,11 @@
; All floating point registers are temporaries for the ilp32 and lp64 ABIs.
-define void @foo() {
-; ILP32-LP64-LABEL: foo:
+; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns
+; something appropriate.
+
+define void @callee() {
+; ILP32-LP64-LABEL: callee:
; ILP32-LP64: # %bb.0:
; ILP32-LP64-NEXT: lui a0, %hi(var)
; ILP32-LP64-NEXT: addi a1, a0, %lo(var)
@@ -82,3 +85,24 @@ define void @foo() {
store volatile [32 x double] %val, [32 x double]* @var
ret void
}
+
+; This function tests that RISCVRegisterInfo::getCallPreservedMask returns
+; something appropriate.
+;
+; For the soft float ABIs, no floating point registers are preserved, and
+; codegen will use only ft0 in the body of caller.
+
+define void @caller() {
+; ILP32-LP64-LABEL: caller:
+; ILP32-LP64-NOT: ft{{[1-9][0-9]*}}
+; ILP32-LP64-NOT: fs{{[0-9]+}}
+; ILP32-LP64-NOT: fa{{[0-9]+}}
+; ILP32-LP64: ret
+; ILP32-LP64-NOT: ft{{[1-9][0-9]*}}
+; ILP32-LP64-NOT: fs{{[0-9]+}}
+; ILP32-LP64-NOT: fa{{[0-9]+}}
+ %val = load [32 x double], [32 x double]* @var
+ call void @callee()
+ store volatile [32 x double] %val, [32 x double]* @var
+ ret void
+}
Modified: llvm/trunk/test/CodeGen/RISCV/callee-saved-gprs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/callee-saved-gprs.ll?rev=356122&r1=356121&r2=356122&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/callee-saved-gprs.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/callee-saved-gprs.ll Thu Mar 14 01:17:44 2019
@@ -9,8 +9,11 @@
@var = global [32 x i32] zeroinitializer
-define void @foo() {
-; RV32I-LABEL: foo:
+; This function tests that RISCVRegisterInfo::getCalleeSavedRegs returns
+; something appropriate.
+
+define void @callee() {
+; RV32I-LABEL: callee:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -80
; RV32I-NEXT: sw s0, 76(sp)
@@ -28,7 +31,7 @@ define void @foo() {
; RV32I-NEXT: lui a0, %hi(var)
; RV32I-NEXT: addi a1, a0, %lo(var)
;
-; RV32I-WITH-FP-LABEL: foo:
+; RV32I-WITH-FP-LABEL: callee:
; RV32I-WITH-FP: # %bb.0:
; RV32I-WITH-FP-NEXT: addi sp, sp, -80
; RV32I-WITH-FP-NEXT: sw ra, 76(sp)
@@ -48,7 +51,7 @@ define void @foo() {
; RV32I-WITH-FP-NEXT: lui a0, %hi(var)
; RV32I-WITH-FP-NEXT: addi a1, a0, %lo(var)
;
-; RV64I-LABEL: foo:
+; RV64I-LABEL: callee:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -144
; RV64I-NEXT: sd s0, 136(sp)
@@ -66,7 +69,7 @@ define void @foo() {
; RV64I-NEXT: lui a0, %hi(var)
; RV64I-NEXT: addi a1, a0, %lo(var)
;
-; RV64I-WITH-FP-LABEL: foo:
+; RV64I-WITH-FP-LABEL: callee:
; RV64I-WITH-FP: # %bb.0:
; RV64I-WITH-FP-NEXT: addi sp, sp, -160
; RV64I-WITH-FP-NEXT: sd ra, 152(sp)
@@ -89,3 +92,126 @@ define void @foo() {
store volatile [32 x i32] %val, [32 x i32]* @var
ret void
}
+
+; This function tests that RISCVRegisterInfo::getCallPreservedMask returns
+; something appropriate.
+
+define void @caller() {
+; RV32I-LABEL: caller:
+; RV32I: lui a0, %hi(var)
+; RV32I-NEXT: addi s1, a0, %lo(var)
+; RV32I: sw a0, 8(sp)
+; RV32I-NEXT: lw s2, 84(s1)
+; RV32I-NEXT: lw s3, 88(s1)
+; RV32I-NEXT: lw s4, 92(s1)
+; RV32I-NEXT: lw s5, 96(s1)
+; RV32I-NEXT: lw s6, 100(s1)
+; RV32I-NEXT: lw s7, 104(s1)
+; RV32I-NEXT: lw s8, 108(s1)
+; RV32I-NEXT: lw s9, 112(s1)
+; RV32I-NEXT: lw s10, 116(s1)
+; RV32I-NEXT: lw s11, 120(s1)
+; RV32I-NEXT: lw s0, 124(s1)
+; RV32I-NEXT: call callee
+; RV32I-NEXT: sw s0, 124(s1)
+; RV32I-NEXT: sw s11, 120(s1)
+; RV32I-NEXT: sw s10, 116(s1)
+; RV32I-NEXT: sw s9, 112(s1)
+; RV32I-NEXT: sw s8, 108(s1)
+; RV32I-NEXT: sw s7, 104(s1)
+; RV32I-NEXT: sw s6, 100(s1)
+; RV32I-NEXT: sw s5, 96(s1)
+; RV32I-NEXT: sw s4, 92(s1)
+; RV32I-NEXT: sw s3, 88(s1)
+; RV32I-NEXT: sw s2, 84(s1)
+; RV32I-NEXT: lw a0, 8(sp)
+;
+; RV32I-WITH-FP-LABEL: caller:
+; RV32I-WITH-FP: addi s0, sp, 144
+; RV32I-WITH-FP-NEXT: lui a0, %hi(var)
+; RV32I-WITH-FP-NEXT: addi s1, a0, %lo(var)
+; RV32I-WITH-FP: sw a0, -140(s0)
+; RV32I-WITH-FP-NEXT: lw s5, 88(s1)
+; RV32I-WITH-FP-NEXT: lw s6, 92(s1)
+; RV32I-WITH-FP-NEXT: lw s7, 96(s1)
+; RV32I-WITH-FP-NEXT: lw s8, 100(s1)
+; RV32I-WITH-FP-NEXT: lw s9, 104(s1)
+; RV32I-WITH-FP-NEXT: lw s10, 108(s1)
+; RV32I-WITH-FP-NEXT: lw s11, 112(s1)
+; RV32I-WITH-FP-NEXT: lw s2, 116(s1)
+; RV32I-WITH-FP-NEXT: lw s3, 120(s1)
+; RV32I-WITH-FP-NEXT: lw s4, 124(s1)
+; RV32I-WITH-FP-NEXT: call callee
+; RV32I-WITH-FP-NEXT: sw s4, 124(s1)
+; RV32I-WITH-FP-NEXT: sw s3, 120(s1)
+; RV32I-WITH-FP-NEXT: sw s2, 116(s1)
+; RV32I-WITH-FP-NEXT: sw s11, 112(s1)
+; RV32I-WITH-FP-NEXT: sw s10, 108(s1)
+; RV32I-WITH-FP-NEXT: sw s9, 104(s1)
+; RV32I-WITH-FP-NEXT: sw s8, 100(s1)
+; RV32I-WITH-FP-NEXT: sw s7, 96(s1)
+; RV32I-WITH-FP-NEXT: sw s6, 92(s1)
+; RV32I-WITH-FP-NEXT: sw s5, 88(s1)
+; RV32I-WITH-FP-NEXT: lw a0, -140(s0)
+;
+; RV64I-LABEL: caller:
+; RV64I: lui a0, %hi(var)
+; RV64I-NEXT: addi s1, a0, %lo(var)
+; RV64I: sd a0, 0(sp)
+; RV64I-NEXT: lw s2, 84(s1)
+; RV64I-NEXT: lw s3, 88(s1)
+; RV64I-NEXT: lw s4, 92(s1)
+; RV64I-NEXT: lw s5, 96(s1)
+; RV64I-NEXT: lw s6, 100(s1)
+; RV64I-NEXT: lw s7, 104(s1)
+; RV64I-NEXT: lw s8, 108(s1)
+; RV64I-NEXT: lw s9, 112(s1)
+; RV64I-NEXT: lw s10, 116(s1)
+; RV64I-NEXT: lw s11, 120(s1)
+; RV64I-NEXT: lw s0, 124(s1)
+; RV64I-NEXT: call callee
+; RV64I-NEXT: sw s0, 124(s1)
+; RV64I-NEXT: sw s11, 120(s1)
+; RV64I-NEXT: sw s10, 116(s1)
+; RV64I-NEXT: sw s9, 112(s1)
+; RV64I-NEXT: sw s8, 108(s1)
+; RV64I-NEXT: sw s7, 104(s1)
+; RV64I-NEXT: sw s6, 100(s1)
+; RV64I-NEXT: sw s5, 96(s1)
+; RV64I-NEXT: sw s4, 92(s1)
+; RV64I-NEXT: sw s3, 88(s1)
+; RV64I-NEXT: sw s2, 84(s1)
+; RV64I-NEXT: ld a0, 0(sp)
+;
+; RV64I-WITH-FP-LABEL: caller:
+; RV64I-WITH-FP: addi s0, sp, 288
+; RV64I-WITH-FP-NEXT: lui a0, %hi(var)
+; RV64I-WITH-FP-NEXT: addi s1, a0, %lo(var)
+; RV64I-WITH-FP: sd a0, -280(s0)
+; RV64I-WITH-FP-NEXT: lw s5, 88(s1)
+; RV64I-WITH-FP-NEXT: lw s6, 92(s1)
+; RV64I-WITH-FP-NEXT: lw s7, 96(s1)
+; RV64I-WITH-FP-NEXT: lw s8, 100(s1)
+; RV64I-WITH-FP-NEXT: lw s9, 104(s1)
+; RV64I-WITH-FP-NEXT: lw s10, 108(s1)
+; RV64I-WITH-FP-NEXT: lw s11, 112(s1)
+; RV64I-WITH-FP-NEXT: lw s2, 116(s1)
+; RV64I-WITH-FP-NEXT: lw s3, 120(s1)
+; RV64I-WITH-FP-NEXT: lw s4, 124(s1)
+; RV64I-WITH-FP-NEXT: call callee
+; RV64I-WITH-FP-NEXT: sw s4, 124(s1)
+; RV64I-WITH-FP-NEXT: sw s3, 120(s1)
+; RV64I-WITH-FP-NEXT: sw s2, 116(s1)
+; RV64I-WITH-FP-NEXT: sw s11, 112(s1)
+; RV64I-WITH-FP-NEXT: sw s10, 108(s1)
+; RV64I-WITH-FP-NEXT: sw s9, 104(s1)
+; RV64I-WITH-FP-NEXT: sw s8, 100(s1)
+; RV64I-WITH-FP-NEXT: sw s7, 96(s1)
+; RV64I-WITH-FP-NEXT: sw s6, 92(s1)
+; RV64I-WITH-FP-NEXT: sw s5, 88(s1)
+; RV64I-WITH-FP-NEXT: ld a0, -280(s0)
+ %val = load [32 x i32], [32 x i32]* @var
+ call void @callee()
+ store volatile [32 x i32] %val, [32 x i32]* @var
+ ret void
+}
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