[PATCH] D59338: MISched: Don't schedule regions with 0 instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: atrick, MatzeB, thegameg, niravd, qcolombet.
Herald added subscribers: jdoerfert, javed.absar, nhaehnle, wdng, jvesely.
arsenm added a parent revision: D59271: MIR: Allow targets to serialize MachineFunctionInfo.

I think this is correct, but may not necessarily be the correct fix
for the assertion I'm really trying to solve. If a scheduling region
was found that only has dbg_value instructions, the RegPressure
tracker would end up in an inconsistent state because it would skip
over any debug instructions and point to an instruction outside of the
scheduling region. It may still be possible for this to happen if
there are some real schedulable instructions between dbg_values, but I
haven't managed to break this.

      

The testcase is extremely sensitive and I'm not sure how to make it
more resistent to future scheduler changes that would avoid stressing
this situation.

See also D59144 <https://reviews.llvm.org/D59144>


https://reviews.llvm.org/D59338

Files:
  lib/CodeGen/MachineScheduler.cpp
  test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir

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