[PATCH] D59310: [PowerPC] Fix issue with inline asm - soft float mode

[Strahinja Petrovic via Phabricator via llvm-commits]

spetrovic created this revision.
spetrovic added reviewers: jhibbits, hfinkel, nemanjai.
Herald added subscribers: llvm-commits, jsji, kbarton, eraman.
Herald added a project: LLVM.

This patch adds checks for inline asm code in soft float mode, if someone tries to put hard float (or altivec) instructions in inline asm in soft float mode, we report an error.


Repository:
  rL LLVM

https://reviews.llvm.org/D59310

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/Driver/ppc-inlineasm-sf.c


Index: clang/test/Driver/ppc-inlineasm-sf.c
===================================================================
--- /dev/null
+++ clang/test/Driver/ppc-inlineasm-sf.c
@@ -0,0 +1,16 @@
+// RUN: not %clang -target powerpc-unknown-linux -O2 -fPIC -m32 -msoft-float %s -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-ERRMSG %s
+int foo ()
+{
+  double x,y;
+  int a;
+  __asm__ ("fctiw %0,%1" : "=f"(x) : "f"(y));
+  // CHECK-ERRMSG:      error: invalid output constraint '=f' in asm
+  // CHECK-ERRMSG-NEXT:  __asm__ ("fctiw %0,%1" : "=f"(x) : "f"(y));
+  __asm__ ("fctiw %0,%1" : "=d"(x) : "d"(y));
+  // CHECK-ERRMSG: error: invalid output constraint '=d' in asm
+  // CHECK-ERRMSG-NEXT: __asm__ ("fctiw %0,%1" : "=d"(x) : "d"(y));
+  __asm__ ("vec_dss %0" : "=v"(a));
+  // CHECK-ERRMSG: error: invalid output constraint '=v' in asm
+  // CHECK-ERRMSG-NEXT: __asm__ ("vec_dss %0" : "=v"(a));
+}
+
Index: clang/lib/Basic/Targets/PPC.h
===================================================================
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -53,6 +53,7 @@
   static const char *const GCCRegNames[];
   static const TargetInfo::GCCRegAlias GCCRegAliases[];
   std::string CPU;
+  enum PPCFloatABI { HardFloat, SoftFloat } FloatABI;
 
   // Target cpu features.
   bool HasAltivec = false;
@@ -183,8 +184,11 @@
       return false;
     case 'O': // Zero
       break;
-    case 'b': // Base register
     case 'f': // Floating point register
+      // Don't use floating point registers on soft float ABI.
+      if (FloatABI == SoftFloat)
+        return false;
+    case 'b': // Base register
       Info.setAllowsRegister();
       break;
     // FIXME: The following are added to allow parsing.
@@ -192,6 +196,10 @@
     // Also, is more specific checking needed?  I.e. specific registers?
     case 'd': // Floating point register (containing 64-bit value)
     case 'v': // Altivec vector register
+      // Don't use floating point and altivec vector registers
+      // on soft float ABI
+      if (FloatABI == SoftFloat)
+        return false;
       Info.setAllowsRegister();
       break;
     case 'w':
Index: clang/lib/Basic/Targets/PPC.cpp
===================================================================
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -30,6 +30,7 @@
 /// configured set of features.
 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
                                          DiagnosticsEngine &Diags) {
+  FloatABI = HardFloat;
   for (const auto &Feature : Features) {
     if (Feature == "+altivec") {
       HasAltivec = true;
@@ -53,6 +54,8 @@
       HasFloat128 = true;
     } else if (Feature == "+power9-vector") {
       HasP9Vector = true;
+    } else if (Feature == "-hard-float") {
+      FloatABI = SoftFloat;
     }
     // TODO: Finish this list and add an assert that we've handled them
     // all.


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