[llvm] r356045 - [mips] Map SW instruction to its microMIPS R6 variant
Simon Atanasyan via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 13 06:09:31 PDT 2019
Author: atanasyan
Date: Wed Mar 13 06:09:30 2019
New Revision: 356045
URL: http://llvm.org/viewvc/llvm-project?rev=356045&view=rev
Log:
[mips] Map SW instruction to its microMIPS R6 variant
To provide mapping between standard and microMIPS R6 variants of the
`sw` command we have to rename SWSP_xxx commands from "sw" to "swsp".
Otherwise `tablegen` starts to show the error `Multiple matches found
for `SW'`. After that to restore printing SWSP command as `sw`, I add
an appropriate `MipsInstAlias` instance.
We also need to implement "size reduction" for microMIPS R6. But this
task is for separate patch. After that the `micromips-lwsp-swsp.ll` test
case will be extended.
Differential Revision: http://reviews.llvm.org/D59046
Added:
llvm/trunk/test/CodeGen/Mips/micromips-sw.ll
Modified:
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Mips/macro-ld-sd.s
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=356045&r1=356044&r2=356045&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Wed Mar 13 06:09:30 2019
@@ -1210,7 +1210,7 @@ class SW16_MMR6_DESC : SB16_MMR6_DESC_BA
class SWSP_MMR6_DESC
: MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
!strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
- MMR6Arch<"sw"> {
+ MMR6Arch<"swsp"> {
let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
let mayStore = 1;
}
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=356045&r1=356044&r2=356045&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Wed Mar 13 06:09:30 2019
@@ -654,7 +654,7 @@ def LWGP_MM : LoadGPMM16<"lw", GPRMM16Op
LOAD_GP_FM_MM16<0x19>, ISA_MICROMIPS;
def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
LOAD_STORE_SP_FM_MM16<0x12>, ISA_MICROMIPS;
-def SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
+def SWSP_MM : StoreSPMM16<"swsp", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
LOAD_STORE_SP_FM_MM16<0x32>, ISA_MICROMIPS32_NOT_MIPS32R6;
def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16,
ISA_MICROMIPS;
@@ -1453,3 +1453,6 @@ def : MipsInstAlias<"mtgc0 $rt, $rs",
def : MipsInstAlias<"mthgc0 $rt, $rs",
(MTHGC0_MM COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
ISA_MICROMIPS32R5, ASE_VIRT;
+def : MipsInstAlias<"sw $rt, $offset",
+ (SWSP_MM GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset), 1>,
+ ISA_MICROMIPS;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=356045&r1=356044&r2=356045&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Mar 13 06:09:30 2019
@@ -2124,7 +2124,7 @@ let AdditionalPredicates = [NotInMicroMi
LW_FM<0x28>, ISA_MIPS1;
def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>,
ISA_MIPS1;
- def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>, ISA_MIPS1;
+ def SW : StdMMR6Rel, Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>, ISA_MIPS1;
}
/// load/store left/right
Added: llvm/trunk/test/CodeGen/Mips/micromips-sw.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips-sw.ll?rev=356045&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips-sw.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/micromips-sw.ll Wed Mar 13 06:09:30 2019
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+micromips \
+; RUN: -filetype=obj -o - %s | llvm-objdump -d - \
+; RUN: | FileCheck --check-prefix=MM2 %s
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs \
+; RUN: -filetype=obj -o - %s | llvm-objdump -d - \
+; RUN: | FileCheck --check-prefix=MM6 %s
+
+define void @fun(i32 %val) {
+; MM2-LABEL: fun:
+; MM2: cb e5 sw $ra, 20($sp)
+
+; MM6-LABEL: fun:
+; MM6: fb fd 00 14 sw $ra, 20($sp)
+entry:
+ call i32* @fun1()
+ ret void
+}
+
+declare i32* @fun1()
Modified: llvm/trunk/test/MC/Mips/macro-ld-sd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/macro-ld-sd.s?rev=356045&r1=356044&r2=356045&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/macro-ld-sd.s (original)
+++ llvm/trunk/test/MC/Mips/macro-ld-sd.s Wed Mar 13 06:09:30 2019
@@ -1,5 +1,9 @@
-# RUN: llvm-mc -triple mips-mti-linux-gnu -show-encoding %s | FileCheck \
-# RUN: --check-prefixes=ALL,32 %s
+# RUN: llvm-mc -triple mips-mti-linux-gnu -mcpu=mips32r2 \
+# RUN: -show-encoding %s | FileCheck --check-prefixes=ALL,32 %s
+# RUN: llvm-mc -triple mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips \
+# RUN: -show-encoding %s | FileCheck --check-prefixes=ALL,MM2 %s
+# RUN: llvm-mc -triple mips-mti-linux-gnu -mcpu=mips32r6 -mattr=+micromips \
+# RUN: -show-encoding %s | FileCheck --check-prefixes=ALL,MM6 %s
# RUN: llvm-mc -triple mips64-mti-linux-gnu -show-encoding %s -target-abi n64 \
# RUN: | FileCheck --check-prefixes=ALL,64 %s
# RUN: llvm-mc -triple mips64-mti-linux-gnu -show-encoding %s -target-abi n32 \
@@ -9,16 +13,32 @@
ld $8, 0($5)
# 32: lw $8, 0($5) # encoding: [0x8c,0xa8,0x00,0x00]
# 32: lw $9, 4($5) # encoding: [0x8c,0xa9,0x00,0x04]
+# MM2: lw $8, 0($5) # encoding: [0xfd,0x05,0x00,0x00]
+# MM2: lw $9, 4($5) # encoding: [0xfd,0x25,0x00,0x04]
+# MM6: lw $8, 0($5) # encoding: [0xfd,0x05,0x00,0x00]
+# MM6: lw $9, 4($5) # encoding: [0xfd,0x25,0x00,0x04]
# 64: ld $8, 0($5) # encoding: [0xdc,0xa8,0x00,0x00]
sd $8, 0($5)
# 32: sw $8, 0($5) # encoding: [0xac,0xa8,0x00,0x00]
# 32: sw $9, 4($5) # encoding: [0xac,0xa9,0x00,0x04]
+# MM2: sw $8, 0($5) # encoding: [0xf9,0x05,0x00,0x00]
+# MM2: sw $9, 4($5) # encoding: [0xf9,0x25,0x00,0x04]
+# MM6: sw $8, 0($5) # encoding: [0xf9,0x05,0x00,0x00]
+# MM6: sw $9, 4($5) # encoding: [0xf9,0x25,0x00,0x04]
# 64: sd $8, 0($5) # encoding: [0xfc,0xa8,0x00,0x00]
ld $8, 0($8)
# 32: lw $9, 4($8) # encoding: [0x8d,0x09,0x00,0x04]
# 32: lw $8, 0($8) # encoding: [0x8d,0x08,0x00,0x00]
+# MM2: lw $9, 4($8) # encoding: [0xfd,0x28,0x00,0x04]
+# MM2: lw $8, 0($8) # encoding: [0xfd,0x08,0x00,0x00]
+# MM6: lw $9, 4($8) # encoding: [0xfd,0x28,0x00,0x04]
+# MM6: lw $8, 0($8) # encoding: [0xfd,0x08,0x00,0x00]
# 64: ld $8, 0($8) # encoding: [0xdd,0x08,0x00,0x00]
sd $8, 0($8)
# 32: sw $8, 0($8) # encoding: [0xad,0x08,0x00,0x00]
# 32: sw $9, 4($8) # encoding: [0xad,0x09,0x00,0x04]
+# MM2: sw $8, 0($8) # encoding: [0xf9,0x08,0x00,0x00]
+# MM2: sw $9, 4($8) # encoding: [0xf9,0x28,0x00,0x04]
+# MM6: sw $8, 0($8) # encoding: [0xf9,0x08,0x00,0x00]
+# MM6: sw $9, 4($8) # encoding: [0xf9,0x28,0x00,0x04]
# 64: sd $8, 0($8) # encoding: [0xfd,0x08,0x00,0x00]
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