[PATCH] D59256: [ARM] Disable LDM with offset for thumb2 cortex-m cpus
Dave Green via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 12 09:36:50 PDT 2019
dmgreen updated this revision to Diff 190282.
dmgreen marked an inline comment as done.
dmgreen added a comment.
Now minsize
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D59256/new/
https://reviews.llvm.org/D59256
Files:
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
llvm/test/CodeGen/Thumb2/ldstopt-addm.ll
Index: llvm/test/CodeGen/Thumb2/ldstopt-addm.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/ldstopt-addm.ll
+++ llvm/test/CodeGen/Thumb2/ldstopt-addm.ll
@@ -22,8 +22,9 @@
;
; CHECK-LABEL: test:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: add.w r3, r0, #48
-; CHECK-NEXT: ldm r3, {r1, r2, r3}
+; CHECK-NEXT: ldr r1, [r0, #48]
+; CHECK-NEXT: ldr r2, [r0, #52]
+; CHECK-NEXT: ldr r3, [r0, #56]
; CHECK-NEXT: ldr r0, [r0, #60]
; CHECK-NEXT: add r0, r3
; CHECK-NEXT: add r1, r2
Index: llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -673,6 +673,10 @@
if (!SafeToClobberCPSR)
return nullptr;
+ // On M class cores, the extra add will only increase latency
+ if (STI->isMClass() && !isThumb1 && !MF->getFunction().optForMinSize())
+ return nullptr;
+
unsigned NewBase;
if (isi32Load(Opcode)) {
// If it is a load, then just use one of the destination registers
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D59256.190282.patch
Type: text/x-patch
Size: 1152 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190312/9b7ddbe1/attachment.bin>
More information about the llvm-commits
mailing list