[PATCH] D59187: [AArch64] Turn BIC creation into a DAG combine

[Nikita Popov via Phabricator via llvm-commits]

nikic added a comment.

In D59187#1424052 <https://reviews.llvm.org/D59187#1424052>, @efriedma wrote:

> I agree it doesn't really make sense to custom-lower this operation.  That said, off the top of my head, I'm not sure why we're doing this at the DAG level at all, given the available instructions; it should be possible to pattern match `(and x, (mvni imm))` during isel.  (If there's some reason that doesn't work, a brief comment explaining it would be helpful.)


My guess would be that this would miss some cases that get lowered to `(and x, (movi imm))`, even though a representation using `mvni` would //also// be possible. The code for lowering constant build vectors first tries movi variants, then mvni, then movi with undef bits and finally mvni with undef bits.


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