[PATCH] D59209: Allow fp as an alias of s0

[Ferran Pallarès Roca via Phabricator via llvm-commits]

fpallares created this revision.
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Herald added subscribers: llvm-commits, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar.
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The RISC-V Assembly Programmer's Manual defines `fp` as another alias of `x8`. However, our tablegen rules only recognise `s0`. This patch adds `fp` as another alias of `x8`. GCC also accepts `fp`.


Repository:
  rL LLVM

https://reviews.llvm.org/D59209

Files:
  lib/Target/RISCV/RISCVRegisterInfo.td
  test/MC/RISCV/rvi-asm-regnames.s


Index: test/MC/RISCV/rvi-asm-regnames.s
===================================================================
--- /dev/null
+++ test/MC/RISCV/rvi-asm-regnames.s
@@ -0,0 +1,13 @@
+# RUN: llvm-mc %s -triple=riscv32 \
+# RUN:     | FileCheck %s
+# RUN: llvm-mc %s -triple=riscv64 \
+# RUN:     | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:     | llvm-objdump -d -r - \
+# RUN:     | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
+# RUN:     | llvm-objdump -d -r - \
+# RUN:     | FileCheck %s
+
+# CHECK: addi s0, s0, -4
+addi fp, fp, -4
Index: lib/Target/RISCV/RISCVRegisterInfo.td
===================================================================
--- lib/Target/RISCV/RISCVRegisterInfo.td
+++ lib/Target/RISCV/RISCVRegisterInfo.td
@@ -55,7 +55,7 @@
   def X6  : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>;
   def X7  : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>;
   }
-  def X8  : RISCVReg<8, "x8", ["s0"]>, DwarfRegNum<[8]>;
+  def X8  : RISCVReg<8, "x8", ["s0", "fp"]>, DwarfRegNum<[8]>;
   def X9  : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>;
   def X10 : RISCVReg<10,"x10", ["a0"]>, DwarfRegNum<[10]>;
   def X11 : RISCVReg<11,"x11", ["a1"]>, DwarfRegNum<[11]>;


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