[PATCH] D59045: [mips] Fix encoding of the `mov.d` command for microMIPS R6

Simon Atanasyan via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Mar 11 06:43:04 PDT 2019


atanasyan updated this revision to Diff 190077.
atanasyan added a comment.

- Select microMIPS R6 <https://reviews.llvm.org/source/compiler-rt/> variant of the `mov.d` instruction in the `MipsSEInstrInfo::copyPhysReg` method.

BTW this variant requires less changes in the source code but I'm concerned a bit that almost all other instructions handled in the `MipsSEInstrInfo::copyPhysReg` are mapped to their microMIPS counterparts by mappings in the `td` files.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59045/new/

https://reviews.llvm.org/D59045

Files:
  llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
  llvm/test/CodeGen/Mips/micromips-mtc-mfc.ll


Index: llvm/test/CodeGen/Mips/micromips-mtc-mfc.ll
===================================================================
--- llvm/test/CodeGen/Mips/micromips-mtc-mfc.ll
+++ llvm/test/CodeGen/Mips/micromips-mtc-mfc.ll
@@ -23,7 +23,7 @@
 ;
 ; MM6-LABEL: foo:
 ; MM6:       # %bb.0: # %entry
-; MM6-NEXT:    mov.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x06]
+; MM6-NEXT:    mov.d $f0, $f12 # encoding: [0x54,0x0c,0x20,0x7b]
 ; MM6-NEXT:    mtc1 $zero, $f1 # encoding: [0x54,0x01,0x28,0x3b]
 ; MM6-NEXT:    mthc1 $zero, $f1 # encoding: [0x54,0x01,0x38,0x3b]
 ; MM6-NEXT:    cmp.ule.d $f1, $f12, $f1 # encoding: [0x54,0x2c,0x09,0xd5]
Index: llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
===================================================================
--- llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -145,7 +145,7 @@
   else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
     Opc = Mips::FMOV_D32;
   else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
-    Opc = Mips::FMOV_D64;
+    Opc = isMicroMips ? Mips::FMOV_D64_MM : Mips::FMOV_D64;
   else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
     if (Mips::GPR64RegClass.contains(SrcReg))
       Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D59045.190077.patch
Type: text/x-patch
Size: 1259 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190311/42cad72a/attachment.bin>


More information about the llvm-commits mailing list