[llvm] r355722 - AMDGPU: Correct DS implementation of areLoadsFromSameBasePtr

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Fri Mar  8 12:30:50 2019
New Revision: 355722

URL: http://llvm.org/viewvc/llvm-project?rev=355722&view=rev
Log:
AMDGPU: Correct DS implementation of areLoadsFromSameBasePtr

This was checking the wrong operands for the base register and the
offsets. The indexes are shifted by the number of output registers
from the machine instruction definition, and the chain is moved to the
end.

Modified:
    llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
    llvm/trunk/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=355722&r1=355721&r2=355722&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Fri Mar  8 12:30:50 2019
@@ -167,7 +167,7 @@ bool SIInstrInfo::areLoadsFromSameBasePt
       return false;
 
     // Check base reg.
-    if (Load0->getOperand(1) != Load1->getOperand(1))
+    if (Load0->getOperand(0) != Load1->getOperand(0))
       return false;
 
     // Check chain.
@@ -181,8 +181,8 @@ bool SIInstrInfo::areLoadsFromSameBasePt
         AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
       return false;
 
-    Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
-    Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
+    Offset0 = cast<ConstantSDNode>(Load0->getOperand(1))->getZExtValue();
+    Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue();
     return true;
   }
 
@@ -232,7 +232,7 @@ bool SIInstrInfo::areLoadsFromSameBasePt
       return false;
 
     // getNamedOperandIdx returns the index for MachineInstrs.  Since they
-    // inlcude the output in the operand list, but SDNodes don't, we need to
+    // include the output in the operand list, but SDNodes don't, we need to
     // subtract the index by one.
     --OffIdx0;
     --OffIdx1;

Modified: llvm/trunk/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll?rev=355722&r1=355721&r2=355722&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll Fri Mar  8 12:30:50 2019
@@ -6,8 +6,8 @@
 
 ; GCN-LABEL: {{^}}ds_combine_nodep
 
-; GCN:      ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27
-; GCN-NEXT: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7 offset1:8
+; GCN: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7 offset1:8
+; GCN-NEXT: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27
 define amdgpu_kernel void @ds_combine_nodep(float addrspace(1)* %out, float addrspace(3)* %inptr) {
 
   %base = bitcast float addrspace(3)* %inptr to i8 addrspace(3)*