[PATCH] D56810: [Mem2Reg] Enable promotion for bitcastable load/store values

[Sergey Dmitriev via Phabricator via llvm-commits]

sdmitriev added a comment.

We need this for the internal product which is based on LLVM and there are reasons why hoisting cannot be done in our case (this is actually a different topic).
But regarding the IR expectations, I do not think there are any restrictions for alloca placement. Consider the following example

  void foo(int x) {
    do {
      alloca(1);
    } while (x--);
  }

It will have the following IR after front end with alloca outside of the entry block

  define dso_local void @foo(i32 %x) #0 {
  entry:
    %x.addr = alloca i32, align 4
    store i32 %x, i32* %x.addr, align 4
    br label %do.body
  
  do.body:                                          ; preds = %do.cond, %entry
    %0 = alloca i8, i64 1, align 16
    br label %do.cond
  
  do.cond:                                          ; preds = %do.body
    %1 = load i32, i32* %x.addr, align 4
    %dec = add nsw i32 %1, -1
    store i32 %dec, i32* %x.addr, align 4
    %tobool = icmp ne i32 %1, 0
    br i1 %tobool, label %do.body, label %do.end
  
  do.end:                                           ; preds = %do.cond
    ret void
  }

BTW, hoisting alloca to the entry block for this example would not be legal, though I think it would still be legal to try registerizing it (for this particular example it does not make sense, but I think it can be modified where it would make sense).


Repository:
  rL LLVM

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