[PATCH] D58927: [ARM] Fixed an assumption of power-of-2 vector MVT

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:12153
   unsigned NumLanes = Op.getValueType().getVectorNumElements();
-  if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) {
+  if (FloatBits != 32 || IntBits > 32 || NumLanes > 4 || NumLanes == 3) {
     // These instructions only exist converting from f32 to i32. We can handle
----------------
Is this more readable? I'm not sure if you need to permit NumLanes == 1 or not.

FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58927/new/

https://reviews.llvm.org/D58927