[PATCH] D59091: [AMDGPU] V_CVT_F32_UBYTE{0,1,2,3} are full rate instructions

[Carl Ritson via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL355671: [AMDGPU] V_CVT_F32_UBYTE{0,1,2,3} are full rate instructions (authored by critson, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D59091?vs=189698&id=189822#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59091/new/

https://reviews.llvm.org/D59091

Files:
  llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td
  llvm/trunk/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
  llvm/trunk/test/CodeGen/AMDGPU/udivrem24.ll


Index: llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td
+++ llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td
@@ -185,13 +185,14 @@
 defm V_CVT_OFF_F32_I4 : VOP1Inst  <"v_cvt_off_f32_i4", VOP1_F32_I32>;
 defm V_CVT_F32_F64 : VOP1Inst <"v_cvt_f32_f64", VOP_F32_F64, fpround>;
 defm V_CVT_F64_F32 : VOP1Inst <"v_cvt_f64_f32", VOP_F64_F32, fpextend>;
+defm V_CVT_U32_F64 : VOP1Inst <"v_cvt_u32_f64", VOP_I32_F64, fp_to_uint>;
+defm V_CVT_F64_U32 : VOP1Inst <"v_cvt_f64_u32", VOP1_F64_I32, uint_to_fp>;
+} // End SchedRW = [WriteQuarterRate32]
+
 defm V_CVT_F32_UBYTE0 : VOP1Inst <"v_cvt_f32_ubyte0", VOP1_F32_I32, AMDGPUcvt_f32_ubyte0>;
 defm V_CVT_F32_UBYTE1 : VOP1Inst <"v_cvt_f32_ubyte1", VOP1_F32_I32, AMDGPUcvt_f32_ubyte1>;
 defm V_CVT_F32_UBYTE2 : VOP1Inst <"v_cvt_f32_ubyte2", VOP1_F32_I32, AMDGPUcvt_f32_ubyte2>;
 defm V_CVT_F32_UBYTE3 : VOP1Inst <"v_cvt_f32_ubyte3", VOP1_F32_I32, AMDGPUcvt_f32_ubyte3>;
-defm V_CVT_U32_F64 : VOP1Inst <"v_cvt_u32_f64", VOP_I32_F64, fp_to_uint>;
-defm V_CVT_F64_U32 : VOP1Inst <"v_cvt_f64_u32", VOP1_F64_I32, uint_to_fp>;
-} // End SchedRW = [WriteQuarterRate32]
 
 defm V_FRACT_F32 : VOP1Inst <"v_fract_f32", VOP_F32_F32, AMDGPUfract>;
 defm V_TRUNC_F32 : VOP1Inst <"v_trunc_f32", VOP_F32_F32, ftrunc>;
Index: llvm/trunk/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
@@ -116,8 +116,8 @@
 ; VI-DAG: v_add_u16_e32
 ; VI-DAG: v_add_u16_e32
 
-; GCN: {{buffer|flat}}_store_dwordx4
-; GCN: {{buffer|flat}}_store_dword
+; GCN-DAG: {{buffer|flat}}_store_dwordx4
+; GCN-DAG: {{buffer|flat}}_store_dword
 
 ; GCN: s_endpgm
 define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %out2, <4 x i8> addrspace(1)* noalias %in) nounwind {
Index: llvm/trunk/test/CodeGen/AMDGPU/udivrem24.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/udivrem24.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/udivrem24.ll
@@ -4,8 +4,8 @@
 
 ; FUNC-LABEL: {{^}}udiv24_i8:
 ; SI: v_cvt_f32_ubyte
-; SI: v_cvt_f32_ubyte
-; SI: v_rcp_iflag_f32
+; SI-DAG: v_cvt_f32_ubyte
+; SI-DAG: v_rcp_iflag_f32
 ; SI: v_cvt_u32_f32
 
 ; EG: UINT_TO_FLT
@@ -176,8 +176,8 @@
 
 ; FUNC-LABEL: {{^}}urem24_i8:
 ; SI: v_cvt_f32_ubyte
-; SI: v_cvt_f32_ubyte
-; SI: v_rcp_iflag_f32
+; SI-DAG: v_cvt_f32_ubyte
+; SI-DAG: v_rcp_iflag_f32
 ; SI: v_cvt_u32_f32
 
 ; EG: UINT_TO_FLT


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