[llvm] r355544 - [X86] Add vector mulo with power of two operand tests; NFC
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 6 12:25:49 PST 2019
Author: nikic
Date: Wed Mar 6 12:25:49 2019
New Revision: 355544
URL: http://llvm.org/viewvc/llvm-project?rev=355544&view=rev
Log:
[X86] Add vector mulo with power of two operand tests; NFC
Added:
llvm/trunk/test/CodeGen/X86/mulo-pow2.ll
Added: llvm/trunk/test/CodeGen/X86/mulo-pow2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mulo-pow2.ll?rev=355544&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/mulo-pow2.ll (added)
+++ llvm/trunk/test/CodeGen/X86/mulo-pow2.ll Wed Mar 6 12:25:49 2019
@@ -0,0 +1,188 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
+
+declare { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32>, <4 x i32>)
+declare { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i32> @umul_v4i32_0(<4 x i32> %a, <4 x i32> %b) nounwind {
+; AVX-LABEL: umul_v4i32_0:
+; AVX: # %bb.0:
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: retq
+ %x = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> zeroinitializer)
+ %y = extractvalue { <4 x i32>, <4 x i1> } %x, 0
+ %z = extractvalue { <4 x i32>, <4 x i1> } %x, 1
+ %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y
+ ret <4 x i32> %u
+}
+
+define <4 x i32> @umul_v4i32_1(<4 x i32> %a, <4 x i32> %b) nounwind {
+; AVX-LABEL: umul_v4i32_1:
+; AVX: # %bb.0:
+; AVX-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; AVX-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1,1,1]
+; AVX-NEXT: vpmuludq %xmm3, %xmm2, %xmm2
+; AVX-NEXT: vpmuludq %xmm3, %xmm0, %xmm3
+; AVX-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
+; AVX-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7]
+; AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3
+; AVX-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+; AVX-NEXT: retq
+ %x = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
+ %y = extractvalue { <4 x i32>, <4 x i1> } %x, 0
+ %z = extractvalue { <4 x i32>, <4 x i1> } %x, 1
+ %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y
+ ret <4 x i32> %u
+}
+
+define <4 x i32> @umul_v4i32_2(<4 x i32> %a, <4 x i32> %b) nounwind {
+; AVX-LABEL: umul_v4i32_2:
+; AVX: # %bb.0:
+; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm2
+; AVX-NEXT: vpmaxud %xmm0, %xmm2, %xmm0
+; AVX-NEXT: vpcmpeqd %xmm0, %xmm2, %xmm0
+; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
+; AVX-NEXT: retq
+ %x = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> <i32 2, i32 2, i32 2, i32 2>)
+ %y = extractvalue { <4 x i32>, <4 x i1> } %x, 0
+ %z = extractvalue { <4 x i32>, <4 x i1> } %x, 1
+ %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y
+ ret <4 x i32> %u
+}
+
+define <4 x i32> @umul_v4i32_8(<4 x i32> %a, <4 x i32> %b) nounwind {
+; AVX-LABEL: umul_v4i32_8:
+; AVX: # %bb.0:
+; AVX-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; AVX-NEXT: vmovdqa {{.*#+}} xmm3 = [8,8,8,8]
+; AVX-NEXT: vpmuludq %xmm3, %xmm2, %xmm2
+; AVX-NEXT: vpmuludq %xmm3, %xmm0, %xmm3
+; AVX-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
+; AVX-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7]
+; AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3
+; AVX-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
+; AVX-NEXT: vpslld $3, %xmm0, %xmm0
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+; AVX-NEXT: retq
+ %x = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> <i32 8, i32 8, i32 8, i32 8>)
+ %y = extractvalue { <4 x i32>, <4 x i1> } %x, 0
+ %z = extractvalue { <4 x i32>, <4 x i1> } %x, 1
+ %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y
+ ret <4 x i32> %u
+}
+
+define <4 x i32> @umul_v4i32_2pow31(<4 x i32> %a, <4 x i32> %b) nounwind {
+; AVX-LABEL: umul_v4i32_2pow31:
+; AVX: # %bb.0:
+; AVX-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; AVX-NEXT: vmovdqa {{.*#+}} xmm3 = [2147483648,2147483648,2147483648,2147483648]
+; AVX-NEXT: vpmuludq %xmm3, %xmm2, %xmm2
+; AVX-NEXT: vpmuludq %xmm3, %xmm0, %xmm3
+; AVX-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
+; AVX-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7]
+; AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3
+; AVX-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
+; AVX-NEXT: vpslld $31, %xmm0, %xmm0
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+; AVX-NEXT: retq
+ %x = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>)
+ %y = extractvalue { <4 x i32>, <4 x i1> } %x, 0
+ %z = extractvalue { <4 x i32>, <4 x i1> } %x, 1
+ %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y
+ ret <4 x i32> %u
+}
+
+define <4 x i32> @smul_v4i32_0(<4 x i32> %a, <4 x i32> %b) nounwind {
+; AVX-LABEL: smul_v4i32_0:
+; AVX: # %bb.0:
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
+; AVX-NEXT: retq
+ %x = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> zeroinitializer)
+ %y = extractvalue { <4 x i32>, <4 x i1> } %x, 0
+ %z = extractvalue { <4 x i32>, <4 x i1> } %x, 1
+ %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y
+ ret <4 x i32> %u
+}
+
+define <4 x i32> @smul_v4i32_1(<4 x i32> %a, <4 x i32> %b) nounwind {
+; AVX-LABEL: smul_v4i32_1:
+; AVX: # %bb.0:
+; AVX-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; AVX-NEXT: vmovdqa {{.*#+}} xmm3 = [1,1,1,1]
+; AVX-NEXT: vpmuldq %xmm3, %xmm2, %xmm2
+; AVX-NEXT: vpmuldq %xmm3, %xmm0, %xmm3
+; AVX-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
+; AVX-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7]
+; AVX-NEXT: vpsrad $31, %xmm0, %xmm3
+; AVX-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+; AVX-NEXT: retq
+ %x = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
+ %y = extractvalue { <4 x i32>, <4 x i1> } %x, 0
+ %z = extractvalue { <4 x i32>, <4 x i1> } %x, 1
+ %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y
+ ret <4 x i32> %u
+}
+
+define <4 x i32> @smul_v4i32_2(<4 x i32> %a, <4 x i32> %b) nounwind {
+; AVX-LABEL: smul_v4i32_2:
+; AVX: # %bb.0:
+; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX-NEXT: vpcmpgtd %xmm0, %xmm2, %xmm3
+; AVX-NEXT: vpcmpeqd %xmm4, %xmm4, %xmm4
+; AVX-NEXT: vpxor %xmm4, %xmm3, %xmm3
+; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vpcmpgtd %xmm0, %xmm2, %xmm2
+; AVX-NEXT: vpxor %xmm4, %xmm2, %xmm2
+; AVX-NEXT: vpcmpeqd %xmm2, %xmm3, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+; AVX-NEXT: retq
+ %x = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> <i32 2, i32 2, i32 2, i32 2>)
+ %y = extractvalue { <4 x i32>, <4 x i1> } %x, 0
+ %z = extractvalue { <4 x i32>, <4 x i1> } %x, 1
+ %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y
+ ret <4 x i32> %u
+}
+
+define <4 x i32> @smul_v4i32_8(<4 x i32> %a, <4 x i32> %b) nounwind {
+; AVX-LABEL: smul_v4i32_8:
+; AVX: # %bb.0:
+; AVX-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; AVX-NEXT: vmovdqa {{.*#+}} xmm3 = [8,8,8,8]
+; AVX-NEXT: vpmuldq %xmm3, %xmm2, %xmm2
+; AVX-NEXT: vpmuldq %xmm3, %xmm0, %xmm3
+; AVX-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
+; AVX-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7]
+; AVX-NEXT: vpslld $3, %xmm0, %xmm0
+; AVX-NEXT: vpsrad $31, %xmm0, %xmm3
+; AVX-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+; AVX-NEXT: retq
+ %x = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> <i32 8, i32 8, i32 8, i32 8>)
+ %y = extractvalue { <4 x i32>, <4 x i1> } %x, 0
+ %z = extractvalue { <4 x i32>, <4 x i1> } %x, 1
+ %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y
+ ret <4 x i32> %u
+}
+
+define <4 x i32> @smul_v4i32_2pow31(<4 x i32> %a, <4 x i32> %b) nounwind {
+; AVX-LABEL: smul_v4i32_2pow31:
+; AVX: # %bb.0:
+; AVX-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; AVX-NEXT: vmovdqa {{.*#+}} xmm3 = [2147483648,2147483648,2147483648,2147483648]
+; AVX-NEXT: vpmuldq %xmm3, %xmm2, %xmm2
+; AVX-NEXT: vpmuldq %xmm3, %xmm0, %xmm3
+; AVX-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
+; AVX-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7]
+; AVX-NEXT: vpslld $31, %xmm0, %xmm0
+; AVX-NEXT: vpsrad $31, %xmm0, %xmm3
+; AVX-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+; AVX-NEXT: retq
+ %x = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> %a, <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>)
+ %y = extractvalue { <4 x i32>, <4 x i1> } %x, 0
+ %z = extractvalue { <4 x i32>, <4 x i1> } %x, 1
+ %u = select <4 x i1> %z, <4 x i32> %b, <4 x i32> %y
+ ret <4 x i32> %u
+}
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