[PATCH] D58957: [AMDGPU] Add an experimental buffer fat pointer address space.

[Neil Henning via Phabricator via llvm-commits]

sheredom marked an inline comment as done.
sheredom added inline comments.


================
Comment at: lib/Target/AMDGPU/AMDGPUTargetMachine.cpp:297
+  // flat, non-integral buffer fat pointers.
     return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
          "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
----------------
arsenm wrote:
> sheredom wrote:
> > arsenm wrote:
> > > Shouldn't this add p7:128?
> > It'd need to be p7:160 - but I'm entirely unsure whether LLVM will drop a lung on a non-power of 2 pointer size.
> Why does it need to be 160? It should be 128 like the descriptor
So for non-swizzable buffer descriptors we want to model it using normal LLVM load/store/atomic instructions, so that we have no intrinsics required for them at all. To model this we need a 160-bit pointer for the 128-bit descriptor + 32-bit offset. This is super important because it means these 160-bit pointers partake in all the normal load/store optimizations without us having to have special cases for whatever new intrinsics we'd have to introduce.

We're trying our best to avoid the need for any new intrinsics (if at all possible, it won't always be possible though).


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58957/new/

https://reviews.llvm.org/D58957