[llvm] r355431 - [Subtarget] Merge ProcSched and ProcDesc arrays in MCSubtargetInfo into a single array.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 5 10:54:38 PST 2019
Author: ctopper
Date: Tue Mar 5 10:54:38 2019
New Revision: 355431
URL: http://llvm.org/viewvc/llvm-project?rev=355431&view=rev
Log:
[Subtarget] Merge ProcSched and ProcDesc arrays in MCSubtargetInfo into a single array.
These arrays are both keyed by CPU name and go into the same tablegenerated file. Merge them so we only need to store keys once.
This also removes a weird space saving quirk where we used the ProcDesc.size() to create to build an ArrayRef for ProcSched.
Differential Revision: https://reviews.llvm.org/D58939
Modified:
llvm/trunk/include/llvm/CodeGen/TargetSubtargetInfo.h
llvm/trunk/include/llvm/MC/MCSubtargetInfo.h
llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp
llvm/trunk/lib/MC/MCSubtargetInfo.cpp
llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp
llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
Modified: llvm/trunk/include/llvm/CodeGen/TargetSubtargetInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetSubtargetInfo.h?rev=355431&r1=355430&r2=355431&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/TargetSubtargetInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetSubtargetInfo.h Tue Mar 5 10:54:38 2019
@@ -64,7 +64,6 @@ protected: // Can only create subclasses
TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF,
ArrayRef<SubtargetSubTypeKV> PD,
- const SubtargetInfoKV *ProcSched,
const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA, const InstrStage *IS,
Modified: llvm/trunk/include/llvm/MC/MCSubtargetInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSubtargetInfo.h?rev=355431&r1=355430&r2=355431&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCSubtargetInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCSubtargetInfo.h Tue Mar 5 10:54:38 2019
@@ -54,6 +54,7 @@ struct SubtargetFeatureKV {
struct SubtargetSubTypeKV {
const char *Key; ///< K-V key string
FeatureBitArray Implies; ///< K-V bit mask
+ const MCSchedModel *SchedModel;
/// Compare routine for std::lower_bound
bool operator<(StringRef S) const {
@@ -67,24 +68,6 @@ struct SubtargetSubTypeKV {
};
//===----------------------------------------------------------------------===//
-
-/// Used to provide key value pairs for CPU and arbitrary pointers.
-struct SubtargetInfoKV {
- const char *Key; ///< K-V key string
- const void *Value; ///< K-V pointer value
-
- /// Compare routine for std::lower_bound
- bool operator<(StringRef S) const {
- return StringRef(Key) < S;
- }
-
- /// Compare routine for std::is_sorted.
- bool operator<(const SubtargetInfoKV &Other) const {
- return StringRef(Key) < StringRef(Other.Key);
- }
-};
-
-//===----------------------------------------------------------------------===//
///
/// Generic base class for all target subtargets.
///
@@ -95,7 +78,6 @@ class MCSubtargetInfo {
ArrayRef<SubtargetSubTypeKV> ProcDesc; // Processor descriptions
// Scheduler machine model
- const SubtargetInfoKV *ProcSchedModels;
const MCWriteProcResEntry *WriteProcResTable;
const MCWriteLatencyEntry *WriteLatencyTable;
const MCReadAdvanceEntry *ReadAdvanceTable;
@@ -111,7 +93,6 @@ public:
MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF,
ArrayRef<SubtargetSubTypeKV> PD,
- const SubtargetInfoKV *ProcSched,
const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA, const InstrStage *IS,
const unsigned *OC, const unsigned *FP);
Modified: llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp?rev=355431&r1=355430&r2=355431&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp Tue Mar 5 10:54:38 2019
@@ -17,10 +17,10 @@ using namespace llvm;
TargetSubtargetInfo::TargetSubtargetInfo(
const Triple &TT, StringRef CPU, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetSubTypeKV> PD,
- const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
+ const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
const InstrStage *IS, const unsigned *OC, const unsigned *FP)
- : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
+ : MCSubtargetInfo(TT, CPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {
}
TargetSubtargetInfo::~TargetSubtargetInfo() = default;
Modified: llvm/trunk/lib/MC/MCSubtargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCSubtargetInfo.cpp?rev=355431&r1=355430&r2=355431&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCSubtargetInfo.cpp (original)
+++ llvm/trunk/lib/MC/MCSubtargetInfo.cpp Tue Mar 5 10:54:38 2019
@@ -176,11 +176,11 @@ void MCSubtargetInfo::setDefaultFeatures
MCSubtargetInfo::MCSubtargetInfo(
const Triple &TT, StringRef C, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetSubTypeKV> PD,
- const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
+ const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
const InstrStage *IS, const unsigned *OC, const unsigned *FP)
: TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
- ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL),
+ WriteProcResTable(WPR), WriteLatencyTable(WL),
ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
InitMCProcessorInfo(CPU, FS);
}
@@ -238,25 +238,21 @@ bool MCSubtargetInfo::checkFeatures(Stri
}
const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
- assert(ProcSchedModels && "Processor machine model not available!");
-
- ArrayRef<SubtargetInfoKV> SchedModels(ProcSchedModels, ProcDesc.size());
-
- assert(std::is_sorted(SchedModels.begin(), SchedModels.end()) &&
+ assert(std::is_sorted(ProcDesc.begin(), ProcDesc.end()) &&
"Processor machine model table is not sorted");
// Find entry
- auto Found =
- std::lower_bound(SchedModels.begin(), SchedModels.end(), CPU);
- if (Found == SchedModels.end() || StringRef(Found->Key) != CPU) {
+ const SubtargetSubTypeKV *CPUEntry = Find(CPU, ProcDesc);
+
+ if (!CPUEntry) {
if (CPU != "help") // Don't error if the user asked for help.
errs() << "'" << CPU
<< "' is not a recognized processor for this target"
<< " (ignoring processor)\n";
return MCSchedModel::GetDefaultSchedModel();
}
- assert(Found->Value && "Missing processor SchedModel value");
- return *(const MCSchedModel *)Found->Value;
+ assert(CPUEntry->SchedModel && "Missing processor SchedModel value");
+ return *CPUEntry->SchedModel;
}
InstrItineraryData
Modified: llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp?rev=355431&r1=355430&r2=355431&view=diff
==============================================================================
--- llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp (original)
+++ llvm/trunk/unittests/CodeGen/MachineInstrTest.cpp Tue Mar 5 10:54:38 2019
@@ -47,7 +47,7 @@ class BogusSubtarget : public TargetSubt
public:
BogusSubtarget(TargetMachine &TM)
: TargetSubtargetInfo(Triple(""), "", "", {}, {}, nullptr, nullptr,
- nullptr, nullptr, nullptr, nullptr, nullptr),
+ nullptr, nullptr, nullptr, nullptr),
FL(), TL(TM) {}
~BogusSubtarget() override {}
Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=355431&r1=355430&r2=355431&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Tue Mar 5 10:54:38 2019
@@ -271,8 +271,10 @@ SubtargetEmitter::CPUKeyValues(raw_ostre
printFeatureMask(OS, FeatureList, FeatureMap);
- // The {{}} is for the "implies" section of this data structure.
- OS << " },\n";
+ // Emit the scheduler model pointer.
+ const std::string &ProcModelName =
+ SchedModels.getModelForProc(Processor).ModelName;
+ OS << ", &" << ProcModelName << " },\n";
}
// End processor table
@@ -1387,33 +1389,6 @@ void SubtargetEmitter::EmitProcessorMode
}
//
-// EmitProcessorLookup - generate cpu name to sched model lookup tables.
-//
-void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) {
- // Gather and sort processor information
- std::vector<Record*> ProcessorList =
- Records.getAllDerivedDefinitions("Processor");
- llvm::sort(ProcessorList, LessRecordFieldName());
-
- // Begin processor->sched model table
- OS << "\n";
- OS << "// Sorted (by key) array of sched model for CPU subtype.\n"
- << "extern const llvm::SubtargetInfoKV " << Target
- << "ProcSchedKV[] = {\n";
- // For each processor
- for (Record *Processor : ProcessorList) {
- StringRef Name = Processor->getValueAsString("Name");
- const std::string &ProcModelName =
- SchedModels.getModelForProc(Processor).ModelName;
-
- // Emit as { "cpu", procinit },
- OS << " { \"" << Name << "\", (const void *)&" << ProcModelName << " },\n";
- }
- // End processor->sched model table
- OS << "};\n";
-}
-
-//
// EmitSchedModel - Emits all scheduling model tables, folding common patterns.
//
void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
@@ -1441,12 +1416,10 @@ void SubtargetEmitter::EmitSchedModel(ra
}
EmitSchedClassTables(SchedTables, OS);
+ OS << "\n#undef DBGFIELD\n";
+
// Emit the processor machine model
EmitProcessorModels(OS);
- // Emit the processor lookup data
- EmitProcessorLookup(OS);
-
- OS << "\n#undef DBGFIELD";
}
static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) {
@@ -1759,12 +1732,11 @@ void SubtargetEmitter::emitGenMCSubtarge
OS << " " << Target << "GenMCSubtargetInfo(const Triple &TT, \n"
<< " StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,\n"
<< " ArrayRef<SubtargetSubTypeKV> PD,\n"
- << " const SubtargetInfoKV *ProcSched,\n"
<< " const MCWriteProcResEntry *WPR,\n"
<< " const MCWriteLatencyEntry *WL,\n"
<< " const MCReadAdvanceEntry *RA, const InstrStage *IS,\n"
<< " const unsigned *OC, const unsigned *FP) :\n"
- << " MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched,\n"
+ << " MCSubtargetInfo(TT, CPU, FS, PF, PD,\n"
<< " WPR, WL, RA, IS, OC, FP) { }\n\n"
<< " unsigned resolveVariantSchedClass(unsigned SchedClass,\n"
<< " const MCInst *MI, unsigned CPUID) const override {\n"
@@ -1824,10 +1796,10 @@ void SubtargetEmitter::run(raw_ostream &
#endif
unsigned NumFeatures = FeatureKeyValues(OS, FeatureMap);
OS << "\n";
- unsigned NumProcs = CPUKeyValues(OS, FeatureMap);
- OS << "\n";
EmitSchedModel(OS);
OS << "\n";
+ unsigned NumProcs = CPUKeyValues(OS, FeatureMap);
+ OS << "\n";
#if 0
OS << "} // end anonymous namespace\n\n";
#endif
@@ -1848,8 +1820,7 @@ void SubtargetEmitter::run(raw_ostream &
else
OS << "None, ";
OS << '\n'; OS.indent(22);
- OS << Target << "ProcSchedKV, "
- << Target << "WriteProcResTable, "
+ OS << Target << "WriteProcResTable, "
<< Target << "WriteLatencyTable, "
<< Target << "ReadAdvanceTable, ";
OS << '\n'; OS.indent(22);
@@ -1916,7 +1887,6 @@ void SubtargetEmitter::run(raw_ostream &
OS << "namespace llvm {\n";
OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n";
OS << "extern const llvm::SubtargetSubTypeKV " << Target << "SubTypeKV[];\n";
- OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcSchedKV[];\n";
OS << "extern const llvm::MCWriteProcResEntry "
<< Target << "WriteProcResTable[];\n";
OS << "extern const llvm::MCWriteLatencyEntry "
@@ -1942,8 +1912,7 @@ void SubtargetEmitter::run(raw_ostream &
else
OS << "None, ";
OS << '\n'; OS.indent(24);
- OS << Target << "ProcSchedKV, "
- << Target << "WriteProcResTable, "
+ OS << Target << "WriteProcResTable, "
<< Target << "WriteLatencyTable, "
<< Target << "ReadAdvanceTable, ";
OS << '\n'; OS.indent(24);
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