[PATCH] D58902: [AMDGPU] Support for v3i32/v3f32

[Tim Renouf via Phabricator via llvm-commits]

tpr marked 2 inline comments as done.
tpr added inline comments.


================
Comment at: lib/Target/AMDGPU/SIInstrInfo.cpp:577
+    // TODO: Copy vec3/vec5 with s_mov_b64s then final s_mov_b32.
+    if (!(RI.getRegSizeInBits(*RC) % 64)) {
       Opcode =  AMDGPU::S_MOV_B64;
----------------
rampitec wrote:
> Does that mean for a v3 we will have 3 s_mov_b32 instead of s_mov_b64 + s_mov_b32? That is suboptimal.
Yes.

I can't find any lit test or graphics shader that attempts to copy a vec3 of sgprs here. Any idea how to provoke it so I can try it?


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58902/new/

https://reviews.llvm.org/D58902