[llvm] r355424 - [X86] Allow 8-bit INC/DEC to be converted to LEA.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 5 10:37:37 PST 2019
Author: ctopper
Date: Tue Mar 5 10:37:37 2019
New Revision: 355424
URL: http://llvm.org/viewvc/llvm-project?rev=355424&view=rev
Log:
[X86] Allow 8-bit INC/DEC to be converted to LEA.
We already do this for 16/32/64 as well as 8-bit add with register/immediate. Might as well do it for 8-bit INC/DEC too.
Differential Revision: https://reviews.llvm.org/D58869
Modified:
llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/test/CodeGen/X86/MergeConsecutiveStores.ll
llvm/trunk/test/CodeGen/X86/copy-eflags.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrArithmetic.td?rev=355424&r1=355423&r2=355424&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrArithmetic.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrArithmetic.td Tue Mar 5 10:37:37 2019
@@ -435,11 +435,10 @@ def X86sub_flag_nocf : PatFrag<(ops node
// TODO: inc/dec is slow for P4, but fast for Pentium-M.
let Defs = [EFLAGS] in {
let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in {
-let CodeSize = 2 in
+let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA.
def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
"inc{b}\t$dst",
[(set GR8:$dst, EFLAGS, (X86add_flag_nocf GR8:$src1, 1))]>;
-let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA.
def INC16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
"inc{w}\t$dst",
[(set GR16:$dst, EFLAGS, (X86add_flag_nocf GR16:$src1, 1))]>,
@@ -483,11 +482,10 @@ let Predicates = [UseIncDec, In64BitMode
} // CodeSize = 2, SchedRW
let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in {
-let CodeSize = 2 in
+let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA.
def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
"dec{b}\t$dst",
[(set GR8:$dst, EFLAGS, (X86sub_flag_nocf GR8:$src1, 1))]>;
-let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA.
def DEC16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
"dec{w}\t$dst",
[(set GR16:$dst, EFLAGS, (X86sub_flag_nocf GR16:$src1, 1))]>,
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=355424&r1=355423&r2=355424&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Mar 5 10:37:37 2019
@@ -761,9 +761,11 @@ MachineInstr *X86InstrInfo::convertToThr
.addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
break;
}
+ case X86::INC8r:
case X86::INC16r:
addRegOffset(MIB, InRegLEA, true, 1);
break;
+ case X86::DEC8r:
case X86::DEC16r:
addRegOffset(MIB, InRegLEA, true, -1);
break;
@@ -945,8 +947,6 @@ X86InstrInfo::convertToThreeAddress(Mach
NewMI = addOffset(MIB, 1);
break;
}
- case X86::INC16r:
- return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
case X86::DEC64r:
case X86::DEC32r: {
assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
@@ -970,7 +970,12 @@ X86InstrInfo::convertToThreeAddress(Mach
break;
}
+ case X86::DEC8r:
+ case X86::INC8r:
+ Is8BitOp = true;
+ LLVM_FALLTHROUGH;
case X86::DEC16r:
+ case X86::INC16r:
return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
case X86::ADD64rr:
case X86::ADD64rr_DB:
Modified: llvm/trunk/test/CodeGen/X86/MergeConsecutiveStores.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/MergeConsecutiveStores.ll?rev=355424&r1=355423&r2=355424&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/MergeConsecutiveStores.ll (original)
+++ llvm/trunk/test/CodeGen/X86/MergeConsecutiveStores.ll Tue Mar 5 10:37:37 2019
@@ -632,7 +632,7 @@ define void @loadStoreBaseIndexOffsetSex
; BWON-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
; BWON-NEXT: movsbq (%rdi,%rcx), %rax
; BWON-NEXT: movzbl (%rdx,%rax), %r9d
-; BWON-NEXT: incb %al
+; BWON-NEXT: leal 1(%rax), %eax
; BWON-NEXT: movsbq %al, %rax
; BWON-NEXT: movzbl (%rdx,%rax), %eax
; BWON-NEXT: movb %r9b, (%rsi,%rcx,2)
@@ -651,7 +651,7 @@ define void @loadStoreBaseIndexOffsetSex
; BWOFF-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
; BWOFF-NEXT: movsbq (%rdi,%rcx), %rax
; BWOFF-NEXT: movb (%rdx,%rax), %r9b
-; BWOFF-NEXT: incb %al
+; BWOFF-NEXT: leal 1(%rax), %eax
; BWOFF-NEXT: movsbq %al, %rax
; BWOFF-NEXT: movb (%rdx,%rax), %al
; BWOFF-NEXT: movb %r9b, (%rsi,%rcx,2)
Modified: llvm/trunk/test/CodeGen/X86/copy-eflags.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/copy-eflags.ll?rev=355424&r1=355423&r2=355424&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/copy-eflags.ll (original)
+++ llvm/trunk/test/CodeGen/X86/copy-eflags.ll Tue Mar 5 10:37:37 2019
@@ -43,19 +43,17 @@ define i32 @test1() nounwind {
;
; X64-LABEL: test1:
; X64: # %bb.0: # %entry
-; X64-NEXT: movb {{.*}}(%rip), %dil
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: incb %al
+; X64-NEXT: movb {{.*}}(%rip), %cl
+; X64-NEXT: leal 1(%rcx), %eax
; X64-NEXT: movb %al, {{.*}}(%rip)
; X64-NEXT: incl {{.*}}(%rip)
-; X64-NEXT: sete %sil
-; X64-NEXT: movb {{.*}}(%rip), %cl
-; X64-NEXT: movl %ecx, %edx
-; X64-NEXT: incb %dl
-; X64-NEXT: cmpb %dil, %cl
+; X64-NEXT: sete %dl
+; X64-NEXT: movb {{.*}}(%rip), %sil
+; X64-NEXT: leal 1(%rsi), %edi
+; X64-NEXT: cmpb %cl, %sil
; X64-NEXT: sete {{.*}}(%rip)
-; X64-NEXT: movb %dl, {{.*}}(%rip)
-; X64-NEXT: testb %sil, %sil
+; X64-NEXT: movb %dil, {{.*}}(%rip)
+; X64-NEXT: testb %dl, %dl
; X64-NEXT: jne .LBB0_2
; X64-NEXT: # %bb.1: # %if.then
; X64-NEXT: pushq %rax
More information about the llvm-commits
mailing list