[PATCH] D58902: [AMDGPU] Support for v3i32/v3f32

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/AMDGPUISelLowering.cpp:1430
+         "More vector elements requested than available!");
+  auto IdxTy = getVectorIdxTy(DAG.getDataLayout());
+  SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N,
----------------
You can just hardcode i32


================
Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:334-335
+  setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3f32, Expand);
+  setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i32, Expand);
+  setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4f32, Expand);
+
----------------
Why do these need to be changed?


================
Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:1332
+        ISD::EXTRACT_SUBVECTOR, SL, NarrowedVT, Val,
+        DAG.getConstant(0, SL, getVectorIdxTy(DAG.getDataLayout())));
+  }
----------------
In the backend you can just hardened the index type to i32


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58902/new/

https://reviews.llvm.org/D58902