[PATCH] D58964: [AMDGPU] Allow MIMG with no uses in adjustWritemask in isel

[David Stuttard via Phabricator via llvm-commits]

dstuttard created this revision.
Herald added subscribers: llvm-commits, t-tye, tpr, yaxunl, nhaehnle, wdng, jvesely, kzhuravl, arsenm.
Herald added a project: LLVM.
dstuttard added reviewers: nhaehnle, tpr.

If an MIMG instruction has managed to get through to adjustWritemask in isel but
has no uses (and doesn't enable TFC) then prevent an assertion by not attempting
to adjust the writemask.

The instruction will be removed anyway.

Change-Id: I9a5dba6bafe1f35ac99c1b73df390936e2ac27a7


Repository:
  rL LLVM

https://reviews.llvm.org/D58964

Files:
  lib/Target/AMDGPU/SIISelLowering.cpp
  test/CodeGen/AMDGPU/img-nouse-adjust.ll


Index: test/CodeGen/AMDGPU/img-nouse-adjust.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/img-nouse-adjust.ll
@@ -0,0 +1,27 @@
+; RUN: llc -march=amdgcn -mcpu=gfx900 -start-before=amdgpu-isel -stop-after=amdgpu-isel -verify-machineinstrs < %s | FileCheck %s --check-prefix=GCN
+
+; We're really just checking for no crashes
+; The feature we're testing for in AdjustWriteMask leaves the image_load as an instruction just post amdgpu-isel
+; In reality, it's hard to get an image intrinsic into AdjustWriteMask with no uses as it will usually get removed
+; first, but it can happen, hence the fix associated with this test
+
+; GCN-LABEL: name: _amdgpu_cs_main
+; GCN-LABEL: bb.0
+; GCN: IMAGE_LOAD_V4_V2
+define amdgpu_cs void @_amdgpu_cs_main() local_unnamed_addr #0 {
+.entry:
+  %0 = tail call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 undef, i32 undef, <8 x i32> undef, i32 0, i32 0) #3
+  call void @llvm.trap()
+  unreachable
+}
+
+; Function Attrs: nounwind readonly
+declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32, i32, i32, <8 x i32>, i32, i32) #1
+
+; Function Attrs: cold noreturn nounwind
+declare void @llvm.trap() #2
+  
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readonly  }
+attributes #2 = { cold noreturn nounwind }
+attributes #3 = { nounwind }
Index: lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- lib/Target/AMDGPU/SIISelLowering.cpp
+++ lib/Target/AMDGPU/SIISelLowering.cpp
@@ -9163,6 +9163,10 @@
   // Don't allow 0 dmask, as hardware assumes one channel enabled.
   bool NoChannels = !NewDmask;
   if (NoChannels) {
+    if (!UsesTFC) {
+      // No uses of the result and not using TFC. Then do nothing.
+      return Node;
+    }
     // If the original dmask has one channel - then nothing to do
     if (OldBitsSet == 1)
       return Node;


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