[llvm] r355384 - [AMDGPU] Omit KILL instructions from hazard recognizer

[David Stuttard via llvm-commits]

Author: dstuttard
Date: Tue Mar  5 02:25:16 2019
New Revision: 355384

URL: http://llvm.org/viewvc/llvm-project?rev=355384&view=rev
Log:
[AMDGPU] Omit KILL instructions from hazard recognizer

Summary:
In some cases the KILL was causing a hazard to be introduced as these were
scheduled into hazard slots, but don't result in an instruction.

KILL shouldn't be considered for hazard recognition.

Change-Id: Ib6d2a2160f8c94cd0ce611ab198c7e4f46aeffcf

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58898

Added:
    llvm/trunk/test/CodeGen/AMDGPU/hazard-kill.mir
Modified:
    llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp?rev=355384&r1=355383&r2=355384&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp Tue Mar  5 02:25:16 2019
@@ -241,9 +241,8 @@ void GCNHazardRecognizer::AdvanceCycle()
   // Do not track non-instructions which do not affect the wait states.
   // If included, these instructions can lead to buffer overflow such that
   // detectable hazards are missed.
-  if (CurrCycleInstr->isImplicitDef())
-    return;
-  else if (CurrCycleInstr->isDebugInstr())
+  if (CurrCycleInstr->isImplicitDef() || CurrCycleInstr->isDebugInstr() ||
+      CurrCycleInstr->isKill())
     return;
 
   unsigned NumWaitStates = TII.getNumWaitStates(*CurrCycleInstr);

Added: llvm/trunk/test/CodeGen/AMDGPU/hazard-kill.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/hazard-kill.mir?rev=355384&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/hazard-kill.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/hazard-kill.mir Tue Mar  5 02:25:16 2019
@@ -0,0 +1,32 @@
+# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-sched %s -o - | FileCheck -check-prefix=GFX90 %s
+
+# This tests that a KILL isn't considered as a valid instruction for a hazard
+# slot (e.g. m0 def followed by V_INTERP for gfx9)
+# The hazard recognizer should mov another instruction into that slot (in this case the S_MOV_B32
+
+--- |
+  define amdgpu_ps void @_amdgpu_ps_main() #0 { ret void }
+...
+---
+# CHECK-LABEL: name: _amdgpu_ps_main
+# CHECK-LABEL: bb.0:
+# GFX90: $m0 = S_MOV_B32 killed renamable $sgpr4
+# GFX90-NEXT: KILL undef renamable $sgpr2
+# GFX90-NEXT: S_MOV_B32 0
+# GFX90-NEXT: V_INTERP_MOV_F32
+name:            _amdgpu_ps_main
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr2, $sgpr3, $sgpr4
+  
+    $sgpr6 = S_MOV_B32 killed $sgpr3
+    renamable $sgpr8_sgpr9_sgpr10_sgpr11 = S_LOAD_DWORDX4_IMM renamable $sgpr6_sgpr7, 16, 0
+    $m0 = S_MOV_B32 killed renamable $sgpr4
+    dead renamable $sgpr0 = KILL undef renamable $sgpr2
+    renamable $vgpr0 = V_INTERP_MOV_F32 2, 0, 0, implicit $m0, implicit $exec
+    renamable $sgpr0 = S_MOV_B32 0
+
+    S_ENDPGM
+
+...