[PATCH] D58902: [AMDGPU] Support for v3i32/v3f32

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D58902#1417139 <https://reviews.llvm.org/D58902#1417139>, @rampitec wrote:

> What happens in asm parser/disasm? I thing these still create bogus v4 operands?


Those should already be using the correct register classes. There were never issues after the DAG with these


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https://reviews.llvm.org/D58902