[PATCH] D58904: [AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics

[Tim Renouf via Phabricator via llvm-commits]

tpr marked an inline comment as done.
tpr added inline comments.


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Comment at: test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll:60
+declare <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32>, i32, i32, i32, i32) #0
+
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arsenm wrote:
> I would just merge these test files with the rest of the base intrinsic tests
I didn't do that for symmetry with the store tests, which can't be merged because x3 is not supported at all in intrinsics on gfx6.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58904/new/

https://reviews.llvm.org/D58904