[PATCH] D58902: [AMDGPU] Support for v3i32/v3f32

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Needs a test for the 96-bit spills. An -O0 test case with a value live across a block should work



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Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:6645
+    if (NumElements == 3 && !Subtarget->hasDwordx3LoadStores())
+      return WidenVectorLoad(Op, DAG);
+    // v3 and v4 loads are supported for private and global memory.
----------------
I think the widening case is missing an alignment check, but that's a pre-existing problem that should be fixed separately


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Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:471
+  (add SGPR_96Regs)> {
+  let AllocationPriority = 3; // XXX - Should this be allocatable?
+}
----------------
Yes, it needs to be allocatable.

The allocation priority of the SGPRs is supposed to be lower than VGPRs, but here it's the same as the VGPR. You might need to shift all of the values around to fix this


Repository:
  rL LLVM

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  https://reviews.llvm.org/D58902/new/

https://reviews.llvm.org/D58902