[llvm] r355305 - [ARM] Fix selection of VLDR.16 instruction with imm offset
Oliver Stannard via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 4 01:17:38 PST 2019
Author: olista01
Date: Mon Mar 4 01:17:38 2019
New Revision: 355305
URL: http://llvm.org/viewvc/llvm-project?rev=355305&view=rev
Log:
[ARM] Fix selection of VLDR.16 instruction with imm offset
The isScaledConstantInRange function takes upper and lower bounds which are
checked after dividing by the scale, so the bounds checks for half, single and
double precision should all be the same. Previously, we had wrong bounds checks
for half precision, so selected an immediate the instructions can't actually
represent.
Differential revision: https://reviews.llvm.org/D58822
Added:
llvm/trunk/test/CodeGen/ARM/fp16-load-store.ll
Modified:
llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=355305&r1=355304&r2=355305&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Mar 4 01:17:38 2019
@@ -119,8 +119,7 @@ public:
SDValue &Offset, SDValue &Opc);
bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
SDValue &Offset, SDValue &Opc);
- bool IsAddressingMode5(SDValue N, SDValue &Base, SDValue &Offset,
- int Lwb, int Upb, bool FP16);
+ bool IsAddressingMode5(SDValue N, SDValue &Base, SDValue &Offset, bool FP16);
bool SelectAddrMode5(SDValue N, SDValue &Base, SDValue &Offset);
bool SelectAddrMode5FP16(SDValue N, SDValue &Base, SDValue &Offset);
bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
@@ -902,7 +901,7 @@ bool ARMDAGToDAGISel::SelectAddrMode3Off
}
bool ARMDAGToDAGISel::IsAddressingMode5(SDValue N, SDValue &Base, SDValue &Offset,
- int Lwb, int Upb, bool FP16) {
+ bool FP16) {
if (!CurDAG->isBaseWithConstantOffset(N)) {
Base = N;
if (N.getOpcode() == ISD::FrameIndex) {
@@ -924,7 +923,7 @@ bool ARMDAGToDAGISel::IsAddressingMode5(
int RHSC;
const int Scale = FP16 ? 2 : 4;
- if (isScaledConstantInRange(N.getOperand(1), Scale, Lwb, Upb, RHSC)) {
+ if (isScaledConstantInRange(N.getOperand(1), Scale, -255, 256, RHSC)) {
Base = N.getOperand(0);
if (Base.getOpcode() == ISD::FrameIndex) {
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
@@ -962,16 +961,12 @@ bool ARMDAGToDAGISel::IsAddressingMode5(
bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
SDValue &Base, SDValue &Offset) {
- int Lwb = -256 + 1;
- int Upb = 256;
- return IsAddressingMode5(N, Base, Offset, Lwb, Upb, /*FP16=*/ false);
+ return IsAddressingMode5(N, Base, Offset, /*FP16=*/ false);
}
bool ARMDAGToDAGISel::SelectAddrMode5FP16(SDValue N,
SDValue &Base, SDValue &Offset) {
- int Lwb = -512 + 1;
- int Upb = 512;
- return IsAddressingMode5(N, Base, Offset, Lwb, Upb, /*FP16=*/ true);
+ return IsAddressingMode5(N, Base, Offset, /*FP16=*/ true);
}
bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
Added: llvm/trunk/test/CodeGen/ARM/fp16-load-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp16-load-store.ll?rev=355305&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fp16-load-store.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/fp16-load-store.ll Mon Mar 4 01:17:38 2019
@@ -0,0 +1,105 @@
+; RUN: llc < %s -mtriple armv8a--none-eabi -mattr=+fullfp16 | FileCheck %s
+
+define void @load_zero(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: load_zero:
+; CHECK: vldr.16 {{s[0-9]+}}, [r0]
+ %arrayidx = getelementptr inbounds half, half* %in, i32 0
+ %load = load half, half* %arrayidx, align 2
+ store half %load, half* %out
+ ret void
+}
+
+define void @load_255(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: load_255:
+; CHECK: vldr.16 {{s[0-9]+}}, [r0, #510]
+ %arrayidx = getelementptr inbounds half, half* %in, i32 255
+ %load = load half, half* %arrayidx, align 2
+ store half %load, half* %out
+ ret void
+}
+
+define void @load_256(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: load_256:
+; CHECK: add [[ADDR:r[0-9]+]], r0, #512
+; CHECK: vldr.16 {{s[0-9]+}}, {{\[}}[[ADDR]]{{\]}}
+ %arrayidx = getelementptr inbounds half, half* %in, i32 256
+ %load = load half, half* %arrayidx, align 2
+ store half %load, half* %out
+ ret void
+}
+
+define void @load_neg_255(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: load_neg_255:
+; CHECK: vldr.16 {{s[0-9]+}}, [r0, #-510]
+ %arrayidx = getelementptr inbounds half, half* %in, i32 -255
+ %load = load half, half* %arrayidx, align 2
+ store half %load, half* %out
+ ret void
+}
+
+define void @load_neg_256(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: load_neg_256:
+; CHECK: sub [[ADDR:r[0-9]+]], r0, #512
+; CHECK: vldr.16 {{s[0-9]+}}, {{\[}}[[ADDR]]{{\]}}
+ %arrayidx = getelementptr inbounds half, half* %in, i32 -256
+ %load = load half, half* %arrayidx, align 2
+ store half %load, half* %out
+ ret void
+}
+
+define void @store_zero(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: store_zero:
+ %load = load half, half* %in, align 2
+; CHECK: vstr.16 {{s[0-9]+}}, [r1]
+ %arrayidx = getelementptr inbounds half, half* %out, i32 0
+ store half %load, half* %arrayidx
+ ret void
+}
+
+define void @store_255(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: store_255:
+ %load = load half, half* %in, align 2
+; CHECK: vstr.16 {{s[0-9]+}}, [r1, #510]
+ %arrayidx = getelementptr inbounds half, half* %out, i32 255
+ store half %load, half* %arrayidx
+ ret void
+}
+
+define void @store_256(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: store_256:
+ %load = load half, half* %in, align 2
+; CHECK: add [[ADDR:r[0-9]+]], r1, #512
+; CHECK: vstr.16 {{s[0-9]+}}, {{\[}}[[ADDR]]{{\]}}
+ %arrayidx = getelementptr inbounds half, half* %out, i32 256
+ store half %load, half* %arrayidx
+ ret void
+}
+
+define void @store_neg_255(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: store_neg_255:
+ %load = load half, half* %in, align 2
+; CHECK: vstr.16 {{s[0-9]+}}, [r1, #-510]
+ %arrayidx = getelementptr inbounds half, half* %out, i32 -255
+ store half %load, half* %arrayidx
+ ret void
+}
+
+define void @store_neg_256(half* %in, half* %out) {
+entry:
+; CHECK-LABEL: store_neg_256:
+ %load = load half, half* %in, align 2
+; CHECK: sub [[ADDR:r[0-9]+]], r1, #512
+; CHECK: vstr.16 {{s[0-9]+}}, {{\[}}[[ADDR]]{{\]}}
+ %arrayidx = getelementptr inbounds half, half* %out, i32 -256
+ store half %load, half* %arrayidx
+ ret void
+}
More information about the llvm-commits
mailing list