[PATCH] D58843: [WIP][MC][RISCV] Allow targets to defer forcing relocations

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill created this revision.
lewis-revill added reviewers: asb, jrtc27, apazos, rogfer01, PkmX.
Herald added subscribers: llvm-commits, jdoerfert, jsji, jocewei, rkruppe, the_o, brucehoult, MartinMosbeck, atanasyan, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, fedor.sergeev, kbarton, javed.absar, nemanjai, sdardis, jyknight.
Herald added a project: LLVM.

This patch modifies the process of recording relocations and applying fixups for a fragment to allow the target to remain undecided about whether or not to force a relocation until all fixups have been evaluated.

Only after the target has been allowed to re-evaluate fixups that have been marked as unknown can the process of recording relocations and applying fixups be run.

      

For RISC-V, this allows us to determine exactly which %pcrel_hi and %pcrel_lo fixups need relocations by ensuring all %pcrel_lo fixups and corresponding %pcrel_hi fixups are correctly matched in this regard.

Notable changes for review:

- Changed return type of `shouldForceRelocation` to `Optional<bool>` in `MCAsmBackend`
- Added `handleUnknownFixups` to `MCAsmBackend`
- Split up `handleFixup` and `evaluateFixup` to `handleUnresolvedFixup`, `evaluateFixupPreTarget` and `evaluateFixup`
- Split up fixup handling code into two distinct passes, one to attempt to evaluate and resolve fixups, and another to report errors, record relocations, and apply fixups, with the target being allowed to intervene for unknown fixups in between the two passes

This patch is work in progress, I'd appreciate feedback on the general approach and disruptiveness of this change.


Repository:
  rL LLVM

https://reviews.llvm.org/D58843

Files:
  include/llvm/MC/MCAsmBackend.h
  include/llvm/MC/MCAssembler.h
  lib/MC/MCAssembler.cpp
  lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
  lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
  lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
  lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
  lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
  lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
  lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
  lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
  lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
  lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

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