[PATCH] D58855: [AArch64] Improve FP16 instruction selection for vector round and vector convert from half instructions

[Abderrazek Zaafrani via Phabricator via llvm-commits]

az created this revision.
az added a reviewer: SjoerdMeijer.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

We currently generate inefficient code for vector rounding and vector convert from half due to minor issues in instruction selection lowering. Fix those issues related to checking for the fullfp16 support (for convert instruction) and initialization (for round instruction).


Repository:
  rL LLVM

https://reviews.llvm.org/D58855

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
  llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll
  llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll

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