[llvm] r355163 - [WebAssembly] Lower SIMD shifts since they are fixed in V8

[Thomas Lively via llvm-commits]

Author: tlively
Date: Thu Feb 28 17:38:54 2019
New Revision: 355163

URL: http://llvm.org/viewvc/llvm-project?rev=355163&view=rev
Log:
[WebAssembly] Lower SIMD shifts since they are fixed in V8

Reviewers: sbc100

Subscribers: dschuff, jgravelle-google, hiraditya, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58800

Modified:
    llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp?rev=355163&r1=355162&r2=355163&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp Thu Feb 28 17:38:54 2019
@@ -1291,11 +1291,6 @@ SDValue WebAssemblyTargetLowering::Lower
   // Only manually lower vector shifts
   assert(Op.getSimpleValueType().isVector());
 
-  // Expand all vector shifts until V8 fixes its implementation
-  // TODO: remove this once V8 is fixed
-  if (!Subtarget->hasUnimplementedSIMD128())
-    return unrollVectorShift(Op, DAG);
-
   // Unroll non-splat vector shifts
   BuildVectorSDNode *ShiftVec;
   SDValue SplatVal;