[llvm] r355020 - [InstCombine] add tests for add+ext+add; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 27 11:27:46 PST 2019
Author: spatel
Date: Wed Feb 27 11:27:45 2019
New Revision: 355020
URL: http://llvm.org/viewvc/llvm-project?rev=355020&view=rev
Log:
[InstCombine] add tests for add+ext+add; NFC
Modified:
llvm/trunk/test/Transforms/InstCombine/add.ll
Modified: llvm/trunk/test/Transforms/InstCombine/add.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/add.ll?rev=355020&r1=355019&r2=355020&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/add.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/add.ll Wed Feb 27 11:27:45 2019
@@ -394,6 +394,92 @@ define i8 @add_nuw_signbit(i8 %x) {
ret i8 %y
}
+define i32 @add_nsw_sext_add(i8 %x) {
+; CHECK-LABEL: @add_nsw_sext_add(
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i8 [[X:%.*]], 42
+; CHECK-NEXT: [[EXT:%.*]] = sext i8 [[ADD]] to i32
+; CHECK-NEXT: [[R:%.*]] = add nsw i32 [[EXT]], 356
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %add = add nsw i8 %x, 42
+ %ext = sext i8 %add to i32
+ %r = add i32 %ext, 356
+ ret i32 %r
+}
+
+define i32 @add_nsw_sext_add_extra_use_1(i8 %x, i32* %p) {
+; CHECK-LABEL: @add_nsw_sext_add_extra_use_1(
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i8 [[X:%.*]], 42
+; CHECK-NEXT: [[EXT:%.*]] = sext i8 [[ADD]] to i32
+; CHECK-NEXT: store i32 [[EXT]], i32* [[P:%.*]], align 4
+; CHECK-NEXT: [[R:%.*]] = add nsw i32 [[EXT]], 356
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %add = add nsw i8 %x, 42
+ %ext = sext i8 %add to i32
+ store i32 %ext, i32* %p
+ %r = add i32 %ext, 356
+ ret i32 %r
+}
+
+define <2 x i32> @add_nsw_sext_add_vec_extra_use_2(<2 x i8> %x, <2 x i8>* %p) {
+; CHECK-LABEL: @add_nsw_sext_add_vec_extra_use_2(
+; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i8> [[X:%.*]], <i8 42, i8 -5>
+; CHECK-NEXT: store <2 x i8> [[ADD]], <2 x i8>* [[P:%.*]], align 2
+; CHECK-NEXT: [[EXT:%.*]] = sext <2 x i8> [[ADD]] to <2 x i32>
+; CHECK-NEXT: [[R:%.*]] = add nsw <2 x i32> [[EXT]], <i32 356, i32 12>
+; CHECK-NEXT: ret <2 x i32> [[R]]
+;
+ %add = add nsw <2 x i8> %x, <i8 42, i8 -5>
+ store <2 x i8> %add, <2 x i8>* %p
+ %ext = sext <2 x i8> %add to <2 x i32>
+ %r = add <2 x i32> %ext, <i32 356, i32 12>
+ ret <2 x i32> %r
+}
+
+define <2 x i32> @add_nuw_zext_add_vec(<2 x i16> %x) {
+; CHECK-LABEL: @add_nuw_zext_add_vec(
+; CHECK-NEXT: [[ADD:%.*]] = add nuw <2 x i16> [[X:%.*]], <i16 -42, i16 5>
+; CHECK-NEXT: [[EXT:%.*]] = zext <2 x i16> [[ADD]] to <2 x i32>
+; CHECK-NEXT: [[R:%.*]] = add nsw <2 x i32> [[EXT]], <i32 356, i32 -12>
+; CHECK-NEXT: ret <2 x i32> [[R]]
+;
+ %add = add nuw <2 x i16> %x, <i16 -42, i16 5>
+ %ext = zext <2 x i16> %add to <2 x i32>
+ %r = add <2 x i32> %ext, <i32 356, i32 -12>
+ ret <2 x i32> %r
+}
+
+define i64 @add_nuw_zext_add_extra_use_1(i8 %x, i64* %p) {
+; CHECK-LABEL: @add_nuw_zext_add_extra_use_1(
+; CHECK-NEXT: [[ADD:%.*]] = add nuw i8 [[X:%.*]], 42
+; CHECK-NEXT: [[EXT:%.*]] = zext i8 [[ADD]] to i64
+; CHECK-NEXT: store i64 [[EXT]], i64* [[P:%.*]], align 4
+; CHECK-NEXT: [[R:%.*]] = add nuw nsw i64 [[EXT]], 356
+; CHECK-NEXT: ret i64 [[R]]
+;
+ %add = add nuw i8 %x, 42
+ %ext = zext i8 %add to i64
+ store i64 %ext, i64* %p
+ %r = add i64 %ext, 356
+ ret i64 %r
+}
+
+define i64 @add_nuw_zext_add_extra_use_2(i8 %x, i8* %p) {
+; CHECK-LABEL: @add_nuw_zext_add_extra_use_2(
+; CHECK-NEXT: [[ADD:%.*]] = add nuw i8 [[X:%.*]], 42
+; CHECK-NEXT: store i8 [[ADD]], i8* [[P:%.*]], align 1
+; CHECK-NEXT: [[EXT:%.*]] = zext i8 [[ADD]] to i64
+; CHECK-NEXT: [[R:%.*]] = add nsw i64 [[EXT]], -356
+; CHECK-NEXT: ret i64 [[R]]
+;
+ %add = add nuw i8 %x, 42
+ store i8 %add, i8* %p
+ %ext = zext i8 %add to i64
+ %r = add i64 %ext, -356
+ ret i64 %r
+}
+
define i1 @test21(i32 %x) {
; CHECK-LABEL: @test21(
; CHECK-NEXT: [[Y:%.*]] = icmp eq i32 [[X:%.*]], 119
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