[PATCH] D58690: [AArch64] Add code size information on isFPImmLegal
Evandro Menezes via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 27 10:49:45 PST 2019
evandro added a comment.
`TargetLoweringBase::isFPImmLegal()` could have a default value of `false` for `ForCodeSize`.
================
Comment at: include/llvm/CodeGen/TargetLowering.h:782
+ virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/,
+ bool /*forCodeSize*/) const {
return false;
----------------
CamelCase.
================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:5386
+bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
+ bool forCodeSize) const {
bool IsLegal = false;
----------------
Ditto.
================
Comment at: lib/Target/AArch64/AArch64ISelLowering.h:290
+ bool isFPImmLegal(const APFloat &Imm, EVT VT,
+ bool forCodeSize) const override;
----------------
Ditto.
================
Comment at: lib/Target/AMDGPU/AMDGPUISelLowering.cpp:643
+bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
+ bool forCodeSize) const {
EVT ScalarVT = VT.getScalarType();
----------------
Ditto.
================
Comment at: lib/Target/AMDGPU/AMDGPUISelLowering.h:165
+ bool isFPImmLegal(const APFloat &Imm, EVT VT,
+ bool forCodeSize) const override;
bool ShouldShrinkFPConstant(EVT VT) const override;
----------------
Ditto.
================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:14370
+bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
+ bool forCodeSize) const {
if (!Subtarget->hasVFP3())
----------------
Ditto.
================
Comment at: lib/Target/ARM/ARMISelLowering.h:482
+ bool isFPImmLegal(const APFloat &Imm, EVT VT,
+ bool forCodeSize) const override;
----------------
Ditto.
================
Comment at: lib/Target/Hexagon/HexagonISelLowering.cpp:2928
+bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
+ bool forCodeSize) const {
return true;
----------------
Ditto.
================
Comment at: lib/Target/Hexagon/HexagonISelLowering.h:288
+ bool isFPImmLegal(const APFloat &Imm, EVT VT,
+ bool forCodeSize) const override;
----------------
Ditto.
================
Comment at: lib/Target/Mips/MipsISelLowering.cpp:4150
+bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
+ bool forCodeSize) const {
if (VT != MVT::f32 && VT != MVT::f64)
----------------
Ditto.
================
Comment at: lib/Target/Mips/MipsISelLowering.h:679
+ bool isFPImmLegal(const APFloat &Imm, EVT VT,
+ bool forCodeSize) const override;
----------------
Ditto.
================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:14326
+bool PPCTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
+ bool forCodeSize) const {
if (!VT.isSimple() || !Subtarget.hasVSX())
----------------
Ditto.
================
Comment at: lib/Target/PowerPC/PPCISelLowering.h:891
+ bool isFPImmLegal(const APFloat &Imm, EVT VT,
+ bool forCodeSize) const override;
----------------
Ditto.
================
Comment at: lib/Target/SystemZ/SystemZISelLowering.cpp:695
+bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
+ bool forCodeSize) const {
// We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
----------------
Ditto.
================
Comment at: lib/Target/SystemZ/SystemZISelLowering.h:404
+ bool isFPImmLegal(const APFloat &Imm, EVT VT,
+ bool forCodeSize) const override;
bool isLegalICmpImmediate(int64_t Imm) const override;
----------------
Ditto.
================
Comment at: lib/Target/X86/X86ISelLowering.cpp:4804
+bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
+ bool forCodeSize) const {
for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
----------------
Ditto.
================
Comment at: lib/Target/X86/X86ISelLowering.h:1013
+ bool isFPImmLegal(const APFloat &Imm, EVT VT,
+ bool forCodeSize) const override;
----------------
Ditto.
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D58690/new/
https://reviews.llvm.org/D58690
More information about the llvm-commits
mailing list