[PATCH] D58460: [AArch64] Optimize floating point materialization

[Evandro Menezes via Phabricator via llvm-commits]

evandro added inline comments.


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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:5407
+  // vs. adrp+ldr (it's one instruction longer, but the movw+movk is fused).
+  // So we limit up to 2 instrdduction at most.
+  if (!IsLegal && (VT == MVT::f64 || VT == MVT::f32)) {
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Perhaps you could check for AArch64Subtarget::hasFuseLiterals() and emit up to 5 instructions, thus including f64, unless optimizing for size.


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  https://reviews.llvm.org/D58460/new/

https://reviews.llvm.org/D58460