[PATCH] D42885: [AMDGPU] intrintrics for byte/short load/store

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:5642-5650
+      // set node opcode if buffer_load_byte/short
+      if (Op.hasOneUse()) {
+        if (M->use_begin()->getOpcode() == ISD::SIGN_EXTEND) {
+          if (LoadVT.getScalarType() == MVT::i8)
+            Opc = AMDGPUISD::BUFFER_LOAD_BYTE;
+          else
+            Opc = AMDGPUISD::BUFFER_LOAD_SHORT;
----------------
rtaylor wrote:
> arsenm wrote:
> > rtaylor wrote:
> > > arsenm wrote:
> > > > You shouldn't be inspecting the users. You can just unconditionally use one or the other. You're going to have to insert a truncate back to the original type at the end anyway. You can then add a separate optimization to fold in the sext_inreg or mask into the buffer like is done for loads
> > > There are four potential options so what do you mean by one or the other? There is BUFFER_LOAD_ubyte/ushort/short/byte for the Opc.
> > You can just unconditionally use load_ubyte/load_ushort. Folding the sign extend in is then a separate optimization on a sext (or more likely a sext_inreg)
> So outputting byte/short based on sign_extend in the tablgen pattern? This won't allow re-use of the existing multiclass without changes.
> 
> I think I remember there being a reason Nicolai and I decided not to do this.
This doesn't change the selection. This is an optimization done in the DAGCombiner


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D42885/new/

https://reviews.llvm.org/D42885