[PATCH] D57601: Seperate volatility and atomicity/ordering in SelectionDAG

[Philip Reames via Phabricator via llvm-commits]

reames updated this revision to Diff 188439.
reames added a comment.
Herald added subscribers: nhaehnle, jvesely.

When preparing to land the approved patch, I discovered one last issue.  Essentially, the previously committed fixes for SystemZ and XCore are insufficient.  Both backends do something odd which is they "lower" an AtomicSDNode into the corresponding *non* atomic LoadSDNode, and then let that be selected in turn.  This results in a LoadSDNode w/an atomic (but non-volatile) memory operand.  None of the DAG combines expect that.  Amusingly, the test which fails actually has correct output (i.e. we DSE an atomic store), but I really want this patch to be non-functional.

The fix is simple: opt both backends out of the change for the moment.  I could do a more fine grained fix, but I'd like to land this as is, specifically to demonstrate that the opt-out works for any downstream backends which are effected.

p.s. Sorry for not noticing this earlier.  I must have not built these backends w/all of the various patches applied.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57601/new/

https://reviews.llvm.org/D57601

Files:
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/Target/SystemZ/SystemZISelLowering.cpp
  lib/Target/SystemZ/SystemZISelLowering.h
  lib/Target/XCore/XCoreISelLowering.cpp
  lib/Target/XCore/XCoreISelLowering.h
  test/CodeGen/AMDGPU/syncscopes.ll

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