[PATCH] D58017: [DAG] Add SimplifyDemandedBits support for BSWAP/BITREVERSE

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon updated this revision to Diff 188350.
RKSimon added a comment.

updated with the new aarch64 tests

- the zext(load()) test fails to recognise the upper bits are zero as it becomes anyext(load())
- the arithmetic ubfx tests do still exercise the rotr(bswap()) combine

just need to address the powerpc regression now


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58017/new/

https://reviews.llvm.org/D58017

Files:
  lib/CodeGen/SelectionDAG/TargetLowering.cpp
  test/CodeGen/AArch64/arm64-rev.ll
  test/CodeGen/AMDGPU/bitreverse.ll
  test/CodeGen/AMDGPU/bswap.ll
  test/CodeGen/PowerPC/pr39478.ll
  test/CodeGen/X86/combine-bitreverse.ll
  test/CodeGen/X86/combine-bswap.ll

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