[llvm] r354863 - [AMDGPU] Regenerate bswap/bitreverse tests.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 26 03:01:08 PST 2019
Author: rksimon
Date: Tue Feb 26 03:01:08 2019
New Revision: 354863
URL: http://llvm.org/viewvc/llvm-project?rev=354863&view=rev
Log:
[AMDGPU] Regenerate bswap/bitreverse tests.
Make codegen changes more obvious in D58017
Modified:
llvm/trunk/test/CodeGen/AMDGPU/bitreverse.ll
llvm/trunk/test/CodeGen/AMDGPU/bswap.ll
Modified: llvm/trunk/test/CodeGen/AMDGPU/bitreverse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/bitreverse.ll?rev=354863&r1=354862&r2=354863&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/bitreverse.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/bitreverse.ll Tue Feb 26 03:01:08 2019
@@ -1,6 +1,7 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=amdgcn-- -verify-machineinstrs | FileCheck %s --check-prefixes=FUNC,SI
+; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=FUNC,FLAT,TONGA
+; RUN: llc < %s -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=FUNC,FLAT,VI
declare i32 @llvm.amdgcn.workitem.id.x() #1
@@ -14,41 +15,140 @@ declare <4 x i32> @llvm.bitreverse.v4i32
declare <2 x i64> @llvm.bitreverse.v2i64(<2 x i64>) #1
declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>) #1
-; FUNC-LABEL: {{^}}s_brev_i16:
-; SI: s_brev_b32
define amdgpu_kernel void @s_brev_i16(i16 addrspace(1)* noalias %out, i16 %val) #0 {
+; SI-LABEL: s_brev_i16:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dword s2, s[0:1], 0xb
+; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_brev_b32 s2, s2
+; SI-NEXT: s_lshr_b32 s4, s2, 16
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; FLAT-LABEL: s_brev_i16:
+; FLAT: ; %bb.0:
+; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
+; FLAT-NEXT: s_load_dword s0, s[0:1], 0x2c
+; FLAT-NEXT: s_mov_b32 s7, 0xf000
+; FLAT-NEXT: s_mov_b32 s6, -1
+; FLAT-NEXT: s_waitcnt lgkmcnt(0)
+; FLAT-NEXT: s_and_b32 s0, s0, 0xffff
+; FLAT-NEXT: s_brev_b32 s0, s0
+; FLAT-NEXT: s_lshr_b32 s0, s0, 16
+; FLAT-NEXT: v_mov_b32_e32 v0, s0
+; FLAT-NEXT: buffer_store_short v0, off, s[4:7], 0
+; FLAT-NEXT: s_endpgm
%brev = call i16 @llvm.bitreverse.i16(i16 %val) #1
store i16 %brev, i16 addrspace(1)* %out
ret void
}
-; FUNC-LABEL: {{^}}v_brev_i16:
-; SI: v_bfrev_b32_e32
define amdgpu_kernel void @v_brev_i16(i16 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %valptr) #0 {
+; SI-LABEL: v_brev_i16:
+; SI: ; %bb.0:
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb
+; SI-NEXT: s_mov_b32 s6, s2
+; SI-NEXT: s_mov_b32 s7, s3
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
+; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_bfrev_b32_e32 v0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; FLAT-LABEL: v_brev_i16:
+; FLAT: ; %bb.0:
+; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
+; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
+; FLAT-NEXT: s_mov_b32 s7, 0xf000
+; FLAT-NEXT: s_mov_b32 s6, -1
+; FLAT-NEXT: s_mov_b32 s2, s6
+; FLAT-NEXT: s_mov_b32 s3, s7
+; FLAT-NEXT: s_waitcnt lgkmcnt(0)
+; FLAT-NEXT: buffer_load_ushort v0, off, s[0:3], 0
+; FLAT-NEXT: s_waitcnt vmcnt(0)
+; FLAT-NEXT: v_bfrev_b32_e32 v0, v0
+; FLAT-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; FLAT-NEXT: buffer_store_short v0, off, s[4:7], 0
+; FLAT-NEXT: s_endpgm
%val = load i16, i16 addrspace(1)* %valptr
%brev = call i16 @llvm.bitreverse.i16(i16 %val) #1
store i16 %brev, i16 addrspace(1)* %out
ret void
}
-; FUNC-LABEL: {{^}}s_brev_i32:
-; SI: s_load_dword [[VAL:s[0-9]+]],
-; SI: s_brev_b32 [[SRESULT:s[0-9]+]], [[VAL]]
-; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
-; SI: buffer_store_dword [[VRESULT]],
-; SI: s_endpgm
define amdgpu_kernel void @s_brev_i32(i32 addrspace(1)* noalias %out, i32 %val) #0 {
+; SI-LABEL: s_brev_i32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dword s2, s[0:1], 0xb
+; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_brev_b32 s4, s2
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; FLAT-LABEL: s_brev_i32:
+; FLAT: ; %bb.0:
+; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
+; FLAT-NEXT: s_load_dword s0, s[0:1], 0x2c
+; FLAT-NEXT: s_mov_b32 s7, 0xf000
+; FLAT-NEXT: s_mov_b32 s6, -1
+; FLAT-NEXT: s_waitcnt lgkmcnt(0)
+; FLAT-NEXT: s_brev_b32 s0, s0
+; FLAT-NEXT: v_mov_b32_e32 v0, s0
+; FLAT-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; FLAT-NEXT: s_endpgm
%brev = call i32 @llvm.bitreverse.i32(i32 %val) #1
store i32 %brev, i32 addrspace(1)* %out
ret void
}
-; FUNC-LABEL: {{^}}v_brev_i32:
-; SI: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]],
-; SI: v_bfrev_b32_e32 [[RESULT:v[0-9]+]], [[VAL]]
-; SI: buffer_store_dword [[RESULT]],
-; SI: s_endpgm
define amdgpu_kernel void @v_brev_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) #0 {
+; SI-LABEL: v_brev_i32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s2, 0
+; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: s_mov_b32 s3, s7
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_bfrev_b32_e32 v0, v0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-NEXT: s_endpgm
+;
+; FLAT-LABEL: v_brev_i32:
+; FLAT: ; %bb.0:
+; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
+; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
+; FLAT-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; FLAT-NEXT: s_mov_b32 s7, 0xf000
+; FLAT-NEXT: s_mov_b32 s6, -1
+; FLAT-NEXT: s_waitcnt lgkmcnt(0)
+; FLAT-NEXT: v_mov_b32_e32 v1, s1
+; FLAT-NEXT: v_add_u32_e32 v0, vcc, s0, v0
+; FLAT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; FLAT-NEXT: flat_load_dword v0, v[0:1]
+; FLAT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; FLAT-NEXT: v_bfrev_b32_e32 v0, v0
+; FLAT-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; FLAT-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
%val = load i32, i32 addrspace(1)* %gep
@@ -57,19 +157,75 @@ define amdgpu_kernel void @v_brev_i32(i3
ret void
}
-; FUNC-LABEL: {{^}}s_brev_v2i32:
-; SI: s_brev_b32
-; SI: s_brev_b32
define amdgpu_kernel void @s_brev_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> %val) #0 {
+; SI-LABEL: s_brev_v2i32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb
+; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_brev_b32 s5, s5
+; SI-NEXT: s_brev_b32 s4, s4
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: v_mov_b32_e32 v1, s5
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; FLAT-LABEL: s_brev_v2i32:
+; FLAT: ; %bb.0:
+; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
+; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
+; FLAT-NEXT: s_mov_b32 s7, 0xf000
+; FLAT-NEXT: s_mov_b32 s6, -1
+; FLAT-NEXT: s_waitcnt lgkmcnt(0)
+; FLAT-NEXT: s_brev_b32 s1, s1
+; FLAT-NEXT: s_brev_b32 s0, s0
+; FLAT-NEXT: v_mov_b32_e32 v0, s0
+; FLAT-NEXT: v_mov_b32_e32 v1, s1
+; FLAT-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; FLAT-NEXT: s_endpgm
%brev = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %val) #1
store <2 x i32> %brev, <2 x i32> addrspace(1)* %out
ret void
}
-; FUNC-LABEL: {{^}}v_brev_v2i32:
-; SI: v_bfrev_b32_e32
-; SI: v_bfrev_b32_e32
define amdgpu_kernel void @v_brev_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) #0 {
+; SI-LABEL: v_brev_v2i32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s2, 0
+; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: s_mov_b32 s3, s7
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 addr64
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_bfrev_b32_e32 v1, v1
+; SI-NEXT: v_bfrev_b32_e32 v0, v0
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-NEXT: s_endpgm
+;
+; FLAT-LABEL: v_brev_v2i32:
+; FLAT: ; %bb.0:
+; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
+; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
+; FLAT-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; FLAT-NEXT: s_mov_b32 s7, 0xf000
+; FLAT-NEXT: s_mov_b32 s6, -1
+; FLAT-NEXT: s_waitcnt lgkmcnt(0)
+; FLAT-NEXT: v_mov_b32_e32 v1, s1
+; FLAT-NEXT: v_add_u32_e32 v0, vcc, s0, v0
+; FLAT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; FLAT-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
+; FLAT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; FLAT-NEXT: v_bfrev_b32_e32 v1, v1
+; FLAT-NEXT: v_bfrev_b32_e32 v0, v0
+; FLAT-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; FLAT-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %valptr, i32 %tid
%val = load <2 x i32>, <2 x i32> addrspace(1)* %gep
@@ -78,16 +234,286 @@ define amdgpu_kernel void @v_brev_v2i32(
ret void
}
-; FUNC-LABEL: {{^}}s_brev_i64:
define amdgpu_kernel void @s_brev_i64(i64 addrspace(1)* noalias %out, i64 %val) #0 {
+; SI-LABEL: s_brev_i64:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_mov_b32 s17, 0xff0000
+; SI-NEXT: s_mov_b32 s3, 0
+; SI-NEXT: s_mov_b32 s13, 0xff00
+; SI-NEXT: s_mov_b32 s22, 0xf0f0f0f
+; SI-NEXT: s_mov_b32 s23, 0xf0f0f0f0
+; SI-NEXT: s_mov_b32 s24, 0x33333333
+; SI-NEXT: s_mov_b32 s25, 0xcccccccc
+; SI-NEXT: s_mov_b32 s26, 0x55555555
+; SI-NEXT: s_mov_b32 s27, 0xaaaaaaaa
+; SI-NEXT: s_mov_b32 s9, s3
+; SI-NEXT: s_mov_b32 s10, s3
+; SI-NEXT: s_mov_b32 s12, s3
+; SI-NEXT: s_mov_b32 s14, s3
+; SI-NEXT: s_mov_b32 s16, s3
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_alignbit_b32 v1, s1, v0, 24
+; SI-NEXT: v_alignbit_b32 v0, s1, v0, 8
+; SI-NEXT: s_lshr_b32 s2, s1, 24
+; SI-NEXT: s_lshr_b32 s8, s1, 8
+; SI-NEXT: s_lshl_b64 s[18:19], s[0:1], 8
+; SI-NEXT: s_lshl_b64 s[20:21], s[0:1], 24
+; SI-NEXT: s_lshl_b32 s15, s0, 24
+; SI-NEXT: s_lshl_b32 s0, s0, 8
+; SI-NEXT: v_and_b32_e32 v1, s17, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xff000000, v0
+; SI-NEXT: s_and_b32 s8, s8, s13
+; SI-NEXT: s_and_b32 s11, s19, 0xff
+; SI-NEXT: s_and_b32 s13, s21, s13
+; SI-NEXT: s_and_b32 s17, s0, s17
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: s_or_b64 s[0:1], s[8:9], s[2:3]
+; SI-NEXT: s_or_b64 s[2:3], s[12:13], s[10:11]
+; SI-NEXT: s_or_b64 s[8:9], s[14:15], s[16:17]
+; SI-NEXT: v_or_b32_e32 v0, s0, v0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: s_or_b64 s[0:1], s[8:9], s[2:3]
+; SI-NEXT: v_or_b32_e32 v2, s0, v0
+; SI-NEXT: v_or_b32_e32 v3, s1, v1
+; SI-NEXT: v_and_b32_e32 v1, s22, v3
+; SI-NEXT: v_and_b32_e32 v0, s22, v2
+; SI-NEXT: v_and_b32_e32 v3, s23, v3
+; SI-NEXT: v_and_b32_e32 v2, s23, v2
+; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 4
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 4
+; SI-NEXT: v_or_b32_e32 v2, v2, v0
+; SI-NEXT: v_or_b32_e32 v3, v3, v1
+; SI-NEXT: v_and_b32_e32 v1, s24, v3
+; SI-NEXT: v_and_b32_e32 v0, s24, v2
+; SI-NEXT: v_and_b32_e32 v3, s25, v3
+; SI-NEXT: v_and_b32_e32 v2, s25, v2
+; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 2
+; SI-NEXT: v_or_b32_e32 v2, v2, v0
+; SI-NEXT: v_or_b32_e32 v3, v3, v1
+; SI-NEXT: v_and_b32_e32 v1, s26, v3
+; SI-NEXT: v_and_b32_e32 v0, s26, v2
+; SI-NEXT: v_and_b32_e32 v3, s27, v3
+; SI-NEXT: v_and_b32_e32 v2, s27, v2
+; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 1
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
+; SI-NEXT: v_or_b32_e32 v1, v3, v1
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-NEXT: s_endpgm
+;
+; FLAT-LABEL: s_brev_i64:
+; FLAT: ; %bb.0:
+; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
+; FLAT-NEXT: s_mov_b32 s3, 0
+; FLAT-NEXT: s_mov_b32 s10, 0xff0000
+; FLAT-NEXT: s_mov_b32 s7, s3
+; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; FLAT-NEXT: s_waitcnt lgkmcnt(0)
+; FLAT-NEXT: v_mov_b32_e32 v0, s4
+; FLAT-NEXT: v_alignbit_b32 v1, s5, v0, 24
+; FLAT-NEXT: v_alignbit_b32 v0, s5, v0, 8
+; FLAT-NEXT: s_bfe_u32 s6, s5, 0x80010
+; FLAT-NEXT: v_and_b32_e32 v1, s10, v1
+; FLAT-NEXT: v_and_b32_e32 v0, 0xff000000, v0
+; FLAT-NEXT: s_lshr_b32 s2, s5, 24
+; FLAT-NEXT: s_lshl_b32 s6, s6, 8
+; FLAT-NEXT: s_or_b64 s[6:7], s[6:7], s[2:3]
+; FLAT-NEXT: v_or_b32_e32 v0, v0, v1
+; FLAT-NEXT: s_lshl_b64 s[8:9], s[4:5], 24
+; FLAT-NEXT: v_or_b32_e32 v0, s6, v0
+; FLAT-NEXT: v_mov_b32_e32 v1, s7
+; FLAT-NEXT: s_lshl_b64 s[6:7], s[4:5], 8
+; FLAT-NEXT: s_lshl_b32 s2, s4, 8
+; FLAT-NEXT: s_and_b32 s7, s7, 0xff
+; FLAT-NEXT: s_mov_b32 s6, s3
+; FLAT-NEXT: s_and_b32 s9, s9, 0xff00
+; FLAT-NEXT: s_mov_b32 s8, s3
+; FLAT-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7]
+; FLAT-NEXT: s_lshl_b32 s9, s4, 24
+; FLAT-NEXT: s_and_b32 s5, s2, s10
+; FLAT-NEXT: s_mov_b32 s4, s3
+; FLAT-NEXT: s_or_b64 s[2:3], s[8:9], s[4:5]
+; FLAT-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
+; FLAT-NEXT: v_or_b32_e32 v2, s2, v0
+; FLAT-NEXT: v_or_b32_e32 v3, s3, v1
+; FLAT-NEXT: s_mov_b32 s2, 0xf0f0f0f
+; FLAT-NEXT: v_and_b32_e32 v1, s2, v3
+; FLAT-NEXT: v_and_b32_e32 v0, s2, v2
+; FLAT-NEXT: s_mov_b32 s2, 0xf0f0f0f0
+; FLAT-NEXT: v_and_b32_e32 v3, s2, v3
+; FLAT-NEXT: v_and_b32_e32 v2, s2, v2
+; FLAT-NEXT: v_lshlrev_b64 v[0:1], 4, v[0:1]
+; FLAT-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3]
+; FLAT-NEXT: s_mov_b32 s2, 0x33333333
+; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
+; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
+; FLAT-NEXT: v_and_b32_e32 v1, s2, v3
+; FLAT-NEXT: v_and_b32_e32 v0, s2, v2
+; FLAT-NEXT: s_mov_b32 s2, 0xcccccccc
+; FLAT-NEXT: v_and_b32_e32 v3, s2, v3
+; FLAT-NEXT: v_and_b32_e32 v2, s2, v2
+; FLAT-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
+; FLAT-NEXT: v_lshrrev_b64 v[2:3], 2, v[2:3]
+; FLAT-NEXT: s_mov_b32 s2, 0x55555555
+; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
+; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
+; FLAT-NEXT: v_and_b32_e32 v1, s2, v3
+; FLAT-NEXT: v_and_b32_e32 v0, s2, v2
+; FLAT-NEXT: s_mov_b32 s2, 0xaaaaaaaa
+; FLAT-NEXT: v_and_b32_e32 v3, s2, v3
+; FLAT-NEXT: v_and_b32_e32 v2, s2, v2
+; FLAT-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; FLAT-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
+; FLAT-NEXT: s_mov_b32 s3, 0xf000
+; FLAT-NEXT: s_mov_b32 s2, -1
+; FLAT-NEXT: v_or_b32_e32 v0, v2, v0
+; FLAT-NEXT: v_or_b32_e32 v1, v3, v1
+; FLAT-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; FLAT-NEXT: s_endpgm
%brev = call i64 @llvm.bitreverse.i64(i64 %val) #1
store i64 %brev, i64 addrspace(1)* %out
ret void
}
-; FUNC-LABEL: {{^}}v_brev_i64:
-; SI-NOT: v_or_b32_e64 v{{[0-9]+}}, 0, 0
define amdgpu_kernel void @v_brev_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %valptr) #0 {
+; SI-LABEL: v_brev_i64:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s2, 0
+; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: s_mov_b32 s3, s7
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 addr64
+; SI-NEXT: s_mov_b32 s0, 0xff0000
+; SI-NEXT: s_mov_b32 s1, 0xff00
+; SI-NEXT: s_mov_b32 s2, 0xf0f0f0f
+; SI-NEXT: s_mov_b32 s3, 0xf0f0f0f0
+; SI-NEXT: s_mov_b32 s8, 0x33333333
+; SI-NEXT: s_mov_b32 s9, 0xcccccccc
+; SI-NEXT: s_mov_b32 s10, 0x55555555
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_mov_b32 s11, 0xaaaaaaaa
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_alignbit_b32 v4, v1, v0, 24
+; SI-NEXT: v_alignbit_b32 v5, v1, v0, 8
+; SI-NEXT: v_lshrrev_b32_e32 v6, 24, v1
+; SI-NEXT: v_lshrrev_b32_e32 v7, 8, v1
+; SI-NEXT: v_lshl_b64 v[2:3], v[0:1], 8
+; SI-NEXT: v_lshl_b64 v[1:2], v[0:1], 24
+; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v0
+; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; SI-NEXT: v_and_b32_e32 v4, s0, v4
+; SI-NEXT: v_and_b32_e32 v5, 0xff000000, v5
+; SI-NEXT: v_and_b32_e32 v7, s1, v7
+; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
+; SI-NEXT: v_and_b32_e32 v2, s1, v2
+; SI-NEXT: v_and_b32_e32 v0, s0, v0
+; SI-NEXT: v_or_b32_e32 v4, v5, v4
+; SI-NEXT: v_or_b32_e32 v5, v7, v6
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_or_b32_e32 v2, v0, v2
+; SI-NEXT: v_and_b32_e32 v1, s2, v2
+; SI-NEXT: v_and_b32_e32 v0, s2, v4
+; SI-NEXT: v_and_b32_e32 v3, s3, v2
+; SI-NEXT: v_and_b32_e32 v2, s3, v4
+; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 4
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 4
+; SI-NEXT: v_or_b32_e32 v3, v3, v1
+; SI-NEXT: v_or_b32_e32 v2, v2, v0
+; SI-NEXT: v_and_b32_e32 v1, s8, v3
+; SI-NEXT: v_and_b32_e32 v0, s8, v2
+; SI-NEXT: v_and_b32_e32 v3, s9, v3
+; SI-NEXT: v_and_b32_e32 v2, s9, v2
+; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 2
+; SI-NEXT: v_or_b32_e32 v3, v3, v1
+; SI-NEXT: v_or_b32_e32 v2, v2, v0
+; SI-NEXT: v_and_b32_e32 v1, s10, v3
+; SI-NEXT: v_and_b32_e32 v0, s10, v2
+; SI-NEXT: v_and_b32_e32 v3, s11, v3
+; SI-NEXT: v_and_b32_e32 v2, s11, v2
+; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 1
+; SI-NEXT: v_or_b32_e32 v1, v3, v1
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-NEXT: s_endpgm
+;
+; FLAT-LABEL: v_brev_i64:
+; FLAT: ; %bb.0:
+; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
+; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
+; FLAT-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; FLAT-NEXT: v_mov_b32_e32 v4, 8
+; FLAT-NEXT: s_mov_b32 s2, 0xff0000
+; FLAT-NEXT: s_mov_b32 s3, 0xf0f0f0f
+; FLAT-NEXT: s_waitcnt lgkmcnt(0)
+; FLAT-NEXT: v_mov_b32_e32 v1, s1
+; FLAT-NEXT: v_add_u32_e32 v0, vcc, s0, v0
+; FLAT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; FLAT-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
+; FLAT-NEXT: s_mov_b32 s0, 0xf0f0f0f0
+; FLAT-NEXT: s_mov_b32 s1, 0x33333333
+; FLAT-NEXT: s_mov_b32 s6, 0xcccccccc
+; FLAT-NEXT: s_mov_b32 s8, 0x55555555
+; FLAT-NEXT: s_mov_b32 s9, 0xaaaaaaaa
+; FLAT-NEXT: s_mov_b32 s7, 0xf000
+; FLAT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; FLAT-NEXT: v_lshlrev_b64 v[2:3], 24, v[0:1]
+; FLAT-NEXT: v_alignbit_b32 v2, v1, v0, 24
+; FLAT-NEXT: v_alignbit_b32 v6, v1, v0, 8
+; FLAT-NEXT: v_lshlrev_b32_sdwa v7, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; FLAT-NEXT: v_lshlrev_b64 v[4:5], 8, v[0:1]
+; FLAT-NEXT: v_lshlrev_b32_e32 v4, 24, v0
+; FLAT-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; FLAT-NEXT: v_and_b32_e32 v2, s2, v2
+; FLAT-NEXT: v_and_b32_e32 v6, 0xff000000, v6
+; FLAT-NEXT: v_and_b32_e32 v0, s2, v0
+; FLAT-NEXT: v_or_b32_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; FLAT-NEXT: v_or_b32_e32 v2, v6, v2
+; FLAT-NEXT: v_and_b32_e32 v3, 0xff00, v3
+; FLAT-NEXT: v_or_b32_e32 v1, v2, v1
+; FLAT-NEXT: v_or_b32_e32 v0, v4, v0
+; FLAT-NEXT: v_or_b32_sdwa v2, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; FLAT-NEXT: v_or_b32_e32 v3, v0, v2
+; FLAT-NEXT: v_and_b32_e32 v0, s3, v1
+; FLAT-NEXT: v_and_b32_e32 v2, s0, v1
+; FLAT-NEXT: v_and_b32_e32 v1, s3, v3
+; FLAT-NEXT: v_and_b32_e32 v3, s0, v3
+; FLAT-NEXT: v_lshlrev_b64 v[0:1], 4, v[0:1]
+; FLAT-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3]
+; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
+; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
+; FLAT-NEXT: v_and_b32_e32 v1, s1, v3
+; FLAT-NEXT: v_and_b32_e32 v0, s1, v2
+; FLAT-NEXT: v_and_b32_e32 v3, s6, v3
+; FLAT-NEXT: v_and_b32_e32 v2, s6, v2
+; FLAT-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
+; FLAT-NEXT: v_lshrrev_b64 v[2:3], 2, v[2:3]
+; FLAT-NEXT: s_mov_b32 s6, -1
+; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
+; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
+; FLAT-NEXT: v_and_b32_e32 v1, s8, v3
+; FLAT-NEXT: v_and_b32_e32 v0, s8, v2
+; FLAT-NEXT: v_and_b32_e32 v3, s9, v3
+; FLAT-NEXT: v_and_b32_e32 v2, s9, v2
+; FLAT-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; FLAT-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
+; FLAT-NEXT: v_or_b32_e32 v1, v3, v1
+; FLAT-NEXT: v_or_b32_e32 v0, v2, v0
+; FLAT-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; FLAT-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr i64, i64 addrspace(1)* %valptr, i32 %tid
%val = load i64, i64 addrspace(1)* %gep
@@ -96,15 +522,486 @@ define amdgpu_kernel void @v_brev_i64(i6
ret void
}
-; FUNC-LABEL: {{^}}s_brev_v2i64:
define amdgpu_kernel void @s_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %val) #0 {
+; SI-LABEL: s_brev_v2i64:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_mov_b32 s25, 0xff0000
+; SI-NEXT: s_mov_b32 s9, 0
+; SI-NEXT: s_mov_b32 s20, 0xff000000
+; SI-NEXT: s_mov_b32 s29, 0xff00
+; SI-NEXT: s_movk_i32 s27, 0xff
+; SI-NEXT: s_mov_b32 s32, 0xf0f0f0f
+; SI-NEXT: s_mov_b32 s33, 0xf0f0f0f0
+; SI-NEXT: s_mov_b32 s34, 0x33333333
+; SI-NEXT: s_mov_b32 s35, 0xcccccccc
+; SI-NEXT: s_mov_b32 s36, 0x55555555
+; SI-NEXT: s_mov_b32 s37, 0xaaaaaaaa
+; SI-NEXT: s_mov_b32 s11, s9
+; SI-NEXT: s_mov_b32 s12, s9
+; SI-NEXT: s_mov_b32 s14, s9
+; SI-NEXT: s_mov_b32 s16, s9
+; SI-NEXT: s_mov_b32 s18, s9
+; SI-NEXT: s_mov_b32 s21, s9
+; SI-NEXT: s_mov_b32 s22, s9
+; SI-NEXT: s_mov_b32 s24, s9
+; SI-NEXT: s_mov_b32 s26, s9
+; SI-NEXT: s_mov_b32 s28, s9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s2
+; SI-NEXT: v_alignbit_b32 v1, s3, v0, 24
+; SI-NEXT: v_alignbit_b32 v0, s3, v0, 8
+; SI-NEXT: s_lshr_b32 s8, s3, 24
+; SI-NEXT: s_lshr_b32 s10, s3, 8
+; SI-NEXT: s_lshl_b32 s13, s2, 24
+; SI-NEXT: s_lshl_b32 s15, s2, 8
+; SI-NEXT: s_lshl_b64 s[30:31], s[2:3], 8
+; SI-NEXT: s_and_b32 s17, s31, s27
+; SI-NEXT: s_lshl_b64 s[2:3], s[2:3], 24
+; SI-NEXT: v_mov_b32_e32 v2, s0
+; SI-NEXT: v_alignbit_b32 v3, s1, v2, 24
+; SI-NEXT: v_alignbit_b32 v2, s1, v2, 8
+; SI-NEXT: s_and_b32 s10, s10, s29
+; SI-NEXT: s_lshr_b32 s30, s1, 8
+; SI-NEXT: s_lshl_b32 s23, s0, 24
+; SI-NEXT: s_and_b32 s15, s15, s25
+; SI-NEXT: s_lshl_b32 s38, s0, 8
+; SI-NEXT: s_and_b32 s19, s3, s29
+; SI-NEXT: s_lshl_b64 s[2:3], s[0:1], 8
+; SI-NEXT: v_and_b32_e32 v0, s20, v0
+; SI-NEXT: v_and_b32_e32 v2, s20, v2
+; SI-NEXT: s_and_b32 s20, s30, s29
+; SI-NEXT: s_lshl_b64 s[30:31], s[0:1], 24
+; SI-NEXT: v_and_b32_e32 v1, s25, v1
+; SI-NEXT: v_and_b32_e32 v3, s25, v3
+; SI-NEXT: s_and_b32 s25, s38, s25
+; SI-NEXT: s_and_b32 s27, s3, s27
+; SI-NEXT: s_and_b32 s29, s31, s29
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: s_or_b64 s[2:3], s[10:11], s[8:9]
+; SI-NEXT: s_or_b64 s[10:11], s[12:13], s[14:15]
+; SI-NEXT: s_or_b64 s[12:13], s[18:19], s[16:17]
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
+; SI-NEXT: s_lshr_b32 s8, s1, 24
+; SI-NEXT: s_or_b64 s[0:1], s[22:23], s[24:25]
+; SI-NEXT: s_or_b64 s[14:15], s[28:29], s[26:27]
+; SI-NEXT: v_or_b32_e32 v0, s2, v0
+; SI-NEXT: v_mov_b32_e32 v2, s3
+; SI-NEXT: s_or_b64 s[2:3], s[10:11], s[12:13]
+; SI-NEXT: s_or_b64 s[8:9], s[20:21], s[8:9]
+; SI-NEXT: s_or_b64 s[0:1], s[0:1], s[14:15]
+; SI-NEXT: v_or_b32_e32 v3, s2, v0
+; SI-NEXT: v_or_b32_e32 v4, s3, v2
+; SI-NEXT: v_or_b32_e32 v5, s8, v1
+; SI-NEXT: v_mov_b32_e32 v0, s9
+; SI-NEXT: v_or_b32_e32 v6, s1, v0
+; SI-NEXT: v_and_b32_e32 v0, s32, v3
+; SI-NEXT: v_and_b32_e32 v1, s32, v4
+; SI-NEXT: v_and_b32_e32 v2, s33, v3
+; SI-NEXT: v_and_b32_e32 v3, s33, v4
+; SI-NEXT: v_or_b32_e32 v5, s0, v5
+; SI-NEXT: v_and_b32_e32 v4, s32, v6
+; SI-NEXT: v_and_b32_e32 v6, s33, v6
+; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 4
+; SI-NEXT: v_lshr_b64 v[7:8], v[2:3], 4
+; SI-NEXT: v_and_b32_e32 v3, s32, v5
+; SI-NEXT: v_and_b32_e32 v5, s33, v5
+; SI-NEXT: v_or_b32_e32 v7, v7, v0
+; SI-NEXT: v_or_b32_e32 v8, v8, v1
+; SI-NEXT: v_lshl_b64 v[0:1], v[3:4], 4
+; SI-NEXT: v_lshr_b64 v[2:3], v[5:6], 4
+; SI-NEXT: v_and_b32_e32 v4, s34, v7
+; SI-NEXT: v_and_b32_e32 v5, s34, v8
+; SI-NEXT: v_and_b32_e32 v6, s35, v7
+; SI-NEXT: v_and_b32_e32 v7, s35, v8
+; SI-NEXT: v_or_b32_e32 v8, v2, v0
+; SI-NEXT: v_or_b32_e32 v9, v3, v1
+; SI-NEXT: v_lshl_b64 v[0:1], v[4:5], 2
+; SI-NEXT: v_lshr_b64 v[2:3], v[6:7], 2
+; SI-NEXT: v_and_b32_e32 v4, s34, v8
+; SI-NEXT: v_and_b32_e32 v5, s34, v9
+; SI-NEXT: v_and_b32_e32 v6, s35, v8
+; SI-NEXT: v_and_b32_e32 v7, s35, v9
+; SI-NEXT: v_or_b32_e32 v8, v2, v0
+; SI-NEXT: v_or_b32_e32 v9, v3, v1
+; SI-NEXT: v_lshl_b64 v[0:1], v[4:5], 2
+; SI-NEXT: v_lshr_b64 v[2:3], v[6:7], 2
+; SI-NEXT: v_and_b32_e32 v4, s36, v8
+; SI-NEXT: v_and_b32_e32 v5, s36, v9
+; SI-NEXT: v_and_b32_e32 v6, s37, v8
+; SI-NEXT: v_and_b32_e32 v7, s37, v9
+; SI-NEXT: v_or_b32_e32 v8, v2, v0
+; SI-NEXT: v_or_b32_e32 v9, v3, v1
+; SI-NEXT: v_lshl_b64 v[0:1], v[4:5], 1
+; SI-NEXT: v_lshr_b64 v[2:3], v[6:7], 1
+; SI-NEXT: v_and_b32_e32 v4, s36, v8
+; SI-NEXT: v_and_b32_e32 v5, s36, v9
+; SI-NEXT: v_and_b32_e32 v6, s37, v8
+; SI-NEXT: v_and_b32_e32 v7, s37, v9
+; SI-NEXT: v_or_b32_e32 v2, v2, v0
+; SI-NEXT: v_or_b32_e32 v3, v3, v1
+; SI-NEXT: v_lshl_b64 v[0:1], v[4:5], 1
+; SI-NEXT: v_lshr_b64 v[4:5], v[6:7], 1
+; SI-NEXT: v_or_b32_e32 v0, v4, v0
+; SI-NEXT: v_or_b32_e32 v1, v5, v1
+; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; SI-NEXT: s_endpgm
+;
+; FLAT-LABEL: s_brev_v2i64:
+; FLAT: ; %bb.0:
+; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
+; FLAT-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x34
+; FLAT-NEXT: s_mov_b32 s9, 0
+; FLAT-NEXT: s_mov_b32 s12, 0xff0000
+; FLAT-NEXT: s_mov_b32 s13, 0xff000000
+; FLAT-NEXT: s_mov_b32 s7, s9
+; FLAT-NEXT: s_waitcnt lgkmcnt(0)
+; FLAT-NEXT: v_mov_b32_e32 v0, s2
+; FLAT-NEXT: v_alignbit_b32 v1, s3, v0, 24
+; FLAT-NEXT: v_alignbit_b32 v0, s3, v0, 8
+; FLAT-NEXT: s_bfe_u32 s6, s3, 0x80010
+; FLAT-NEXT: v_and_b32_e32 v1, s12, v1
+; FLAT-NEXT: v_and_b32_e32 v0, s13, v0
+; FLAT-NEXT: s_lshr_b32 s8, s3, 24
+; FLAT-NEXT: s_lshl_b32 s6, s6, 8
+; FLAT-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
+; FLAT-NEXT: v_or_b32_e32 v0, v0, v1
+; FLAT-NEXT: s_lshl_b32 s8, s2, 8
+; FLAT-NEXT: v_or_b32_e32 v0, s6, v0
+; FLAT-NEXT: v_mov_b32_e32 v1, s7
+; FLAT-NEXT: s_and_b32 s11, s8, s12
+; FLAT-NEXT: s_lshl_b32 s7, s2, 24
+; FLAT-NEXT: s_mov_b32 s6, s9
+; FLAT-NEXT: s_mov_b32 s10, s9
+; FLAT-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
+; FLAT-NEXT: s_lshl_b64 s[10:11], s[2:3], 8
+; FLAT-NEXT: s_movk_i32 s14, 0xff
+; FLAT-NEXT: s_lshl_b64 s[2:3], s[2:3], 24
+; FLAT-NEXT: s_mov_b32 s15, 0xff00
+; FLAT-NEXT: s_and_b32 s11, s11, s14
+; FLAT-NEXT: s_mov_b32 s10, s9
+; FLAT-NEXT: s_and_b32 s3, s3, s15
+; FLAT-NEXT: s_mov_b32 s2, s9
+; FLAT-NEXT: s_or_b64 s[2:3], s[2:3], s[10:11]
+; FLAT-NEXT: s_or_b64 s[2:3], s[6:7], s[2:3]
+; FLAT-NEXT: v_mov_b32_e32 v4, s0
+; FLAT-NEXT: v_alignbit_b32 v5, s1, v4, 24
+; FLAT-NEXT: v_alignbit_b32 v4, s1, v4, 8
+; FLAT-NEXT: v_or_b32_e32 v2, s2, v0
+; FLAT-NEXT: s_bfe_u32 s2, s1, 0x80010
+; FLAT-NEXT: v_or_b32_e32 v3, s3, v1
+; FLAT-NEXT: v_and_b32_e32 v5, s12, v5
+; FLAT-NEXT: v_and_b32_e32 v4, s13, v4
+; FLAT-NEXT: s_lshr_b32 s8, s1, 24
+; FLAT-NEXT: s_lshl_b32 s2, s2, 8
+; FLAT-NEXT: s_mov_b32 s3, s9
+; FLAT-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
+; FLAT-NEXT: v_or_b32_e32 v4, v4, v5
+; FLAT-NEXT: s_lshl_b32 s8, s0, 8
+; FLAT-NEXT: v_or_b32_e32 v4, s2, v4
+; FLAT-NEXT: v_mov_b32_e32 v5, s3
+; FLAT-NEXT: s_lshl_b32 s3, s0, 24
+; FLAT-NEXT: s_mov_b32 s2, s9
+; FLAT-NEXT: s_and_b32 s11, s8, s12
+; FLAT-NEXT: s_mov_b32 s16, 0xf0f0f0f
+; FLAT-NEXT: s_or_b64 s[2:3], s[2:3], s[10:11]
+; FLAT-NEXT: s_lshl_b64 s[10:11], s[0:1], 8
+; FLAT-NEXT: s_lshl_b64 s[0:1], s[0:1], 24
+; FLAT-NEXT: s_mov_b32 s17, 0xf0f0f0f0
+; FLAT-NEXT: v_and_b32_e32 v0, s16, v2
+; FLAT-NEXT: v_and_b32_e32 v1, s16, v3
+; FLAT-NEXT: v_and_b32_e32 v2, s17, v2
+; FLAT-NEXT: v_and_b32_e32 v3, s17, v3
+; FLAT-NEXT: s_and_b32 s11, s11, s14
+; FLAT-NEXT: s_mov_b32 s10, s9
+; FLAT-NEXT: s_and_b32 s1, s1, s15
+; FLAT-NEXT: s_mov_b32 s0, s9
+; FLAT-NEXT: s_or_b64 s[0:1], s[0:1], s[10:11]
+; FLAT-NEXT: v_lshlrev_b64 v[0:1], 4, v[0:1]
+; FLAT-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3]
+; FLAT-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
+; FLAT-NEXT: v_or_b32_e32 v6, s0, v4
+; FLAT-NEXT: v_or_b32_e32 v7, s1, v5
+; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
+; FLAT-NEXT: s_mov_b32 s18, 0x33333333
+; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
+; FLAT-NEXT: s_mov_b32 s19, 0xcccccccc
+; FLAT-NEXT: v_and_b32_e32 v0, s18, v2
+; FLAT-NEXT: v_and_b32_e32 v1, s18, v3
+; FLAT-NEXT: v_and_b32_e32 v4, s16, v6
+; FLAT-NEXT: v_and_b32_e32 v5, s16, v7
+; FLAT-NEXT: v_and_b32_e32 v2, s19, v2
+; FLAT-NEXT: v_and_b32_e32 v3, s19, v3
+; FLAT-NEXT: v_and_b32_e32 v6, s17, v6
+; FLAT-NEXT: v_and_b32_e32 v7, s17, v7
+; FLAT-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
+; FLAT-NEXT: v_lshrrev_b64 v[2:3], 2, v[2:3]
+; FLAT-NEXT: v_lshlrev_b64 v[4:5], 4, v[4:5]
+; FLAT-NEXT: v_lshrrev_b64 v[6:7], 4, v[6:7]
+; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
+; FLAT-NEXT: v_or_b32_e32 v6, v6, v4
+; FLAT-NEXT: v_or_b32_e32 v7, v7, v5
+; FLAT-NEXT: s_mov_b32 s20, 0x55555555
+; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
+; FLAT-NEXT: s_mov_b32 s21, 0xaaaaaaaa
+; FLAT-NEXT: v_and_b32_e32 v0, s20, v2
+; FLAT-NEXT: v_and_b32_e32 v1, s20, v3
+; FLAT-NEXT: v_and_b32_e32 v4, s18, v6
+; FLAT-NEXT: v_and_b32_e32 v5, s18, v7
+; FLAT-NEXT: v_and_b32_e32 v2, s21, v2
+; FLAT-NEXT: v_and_b32_e32 v3, s21, v3
+; FLAT-NEXT: v_and_b32_e32 v6, s19, v6
+; FLAT-NEXT: v_and_b32_e32 v7, s19, v7
+; FLAT-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; FLAT-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
+; FLAT-NEXT: v_lshlrev_b64 v[4:5], 2, v[4:5]
+; FLAT-NEXT: v_lshrrev_b64 v[6:7], 2, v[6:7]
+; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
+; FLAT-NEXT: v_or_b32_e32 v0, v6, v4
+; FLAT-NEXT: v_or_b32_e32 v7, v7, v5
+; FLAT-NEXT: v_and_b32_e32 v5, s20, v7
+; FLAT-NEXT: v_and_b32_e32 v4, s20, v0
+; FLAT-NEXT: v_and_b32_e32 v6, s21, v0
+; FLAT-NEXT: v_and_b32_e32 v7, s21, v7
+; FLAT-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
+; FLAT-NEXT: v_lshrrev_b64 v[6:7], 1, v[6:7]
+; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
+; FLAT-NEXT: s_mov_b32 s7, 0xf000
+; FLAT-NEXT: s_mov_b32 s6, -1
+; FLAT-NEXT: v_or_b32_e32 v0, v6, v4
+; FLAT-NEXT: v_or_b32_e32 v1, v7, v5
+; FLAT-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; FLAT-NEXT: s_endpgm
%brev = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %val) #1
store <2 x i64> %brev, <2 x i64> addrspace(1)* %out
ret void
}
-; FUNC-LABEL: {{^}}v_brev_v2i64:
define amdgpu_kernel void @v_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %valptr) #0 {
+; SI-LABEL: v_brev_v2i64:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s2, 0
+; SI-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: s_mov_b32 s3, s7
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 addr64
+; SI-NEXT: s_mov_b32 s0, 0xff0000
+; SI-NEXT: s_mov_b32 s1, 0xff000000
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_alignbit_b32 v8, v3, v2, 24
+; SI-NEXT: v_alignbit_b32 v9, v3, v2, 8
+; SI-NEXT: v_lshrrev_b32_e32 v10, 8, v3
+; SI-NEXT: v_lshl_b64 v[4:5], v[2:3], 8
+; SI-NEXT: v_lshl_b64 v[6:7], v[2:3], 24
+; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v2
+; SI-NEXT: v_alignbit_b32 v6, v1, v0, 24
+; SI-NEXT: v_alignbit_b32 v11, v1, v0, 8
+; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v1
+; SI-NEXT: v_lshrrev_b32_e32 v13, 24, v3
+; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v2
+; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v1
+; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v0
+; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v0
+; SI-NEXT: v_lshl_b64 v[2:3], v[0:1], 8
+; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 24
+; SI-NEXT: s_mov_b32 s2, 0xff00
+; SI-NEXT: s_movk_i32 s3, 0xff
+; SI-NEXT: s_mov_b32 s8, 0xf0f0f0f
+; SI-NEXT: s_mov_b32 s9, 0xf0f0f0f0
+; SI-NEXT: s_mov_b32 s10, 0x33333333
+; SI-NEXT: s_mov_b32 s11, 0xcccccccc
+; SI-NEXT: s_mov_b32 s12, 0x55555555
+; SI-NEXT: s_mov_b32 s13, 0xaaaaaaaa
+; SI-NEXT: v_and_b32_e32 v0, s0, v8
+; SI-NEXT: v_and_b32_e32 v2, s1, v9
+; SI-NEXT: v_and_b32_e32 v8, s2, v10
+; SI-NEXT: v_and_b32_e32 v5, s3, v5
+; SI-NEXT: v_and_b32_e32 v7, s2, v7
+; SI-NEXT: v_and_b32_e32 v4, s0, v4
+; SI-NEXT: v_and_b32_e32 v6, s0, v6
+; SI-NEXT: v_and_b32_e32 v9, s1, v11
+; SI-NEXT: v_and_b32_e32 v10, s2, v12
+; SI-NEXT: v_and_b32_e32 v3, s3, v3
+; SI-NEXT: v_and_b32_e32 v1, s2, v1
+; SI-NEXT: v_and_b32_e32 v11, s0, v17
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
+; SI-NEXT: v_or_b32_e32 v2, v8, v13
+; SI-NEXT: v_or_b32_e32 v5, v7, v5
+; SI-NEXT: v_or_b32_e32 v4, v14, v4
+; SI-NEXT: v_or_b32_e32 v6, v9, v6
+; SI-NEXT: v_or_b32_e32 v7, v10, v15
+; SI-NEXT: v_or_b32_e32 v1, v1, v3
+; SI-NEXT: v_or_b32_e32 v3, v16, v11
+; SI-NEXT: v_or_b32_e32 v2, v0, v2
+; SI-NEXT: v_or_b32_e32 v4, v4, v5
+; SI-NEXT: v_or_b32_e32 v6, v6, v7
+; SI-NEXT: v_or_b32_e32 v7, v3, v1
+; SI-NEXT: v_and_b32_e32 v1, s8, v4
+; SI-NEXT: v_and_b32_e32 v0, s8, v2
+; SI-NEXT: v_and_b32_e32 v3, s9, v4
+; SI-NEXT: v_and_b32_e32 v2, s9, v2
+; SI-NEXT: v_and_b32_e32 v5, s8, v7
+; SI-NEXT: v_and_b32_e32 v4, s8, v6
+; SI-NEXT: v_and_b32_e32 v7, s9, v7
+; SI-NEXT: v_and_b32_e32 v6, s9, v6
+; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 4
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 4
+; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 4
+; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 4
+; SI-NEXT: v_or_b32_e32 v3, v3, v1
+; SI-NEXT: v_or_b32_e32 v2, v2, v0
+; SI-NEXT: v_or_b32_e32 v7, v7, v5
+; SI-NEXT: v_or_b32_e32 v6, v6, v4
+; SI-NEXT: v_and_b32_e32 v1, s10, v3
+; SI-NEXT: v_and_b32_e32 v0, s10, v2
+; SI-NEXT: v_and_b32_e32 v3, s11, v3
+; SI-NEXT: v_and_b32_e32 v2, s11, v2
+; SI-NEXT: v_and_b32_e32 v5, s10, v7
+; SI-NEXT: v_and_b32_e32 v4, s10, v6
+; SI-NEXT: v_and_b32_e32 v7, s11, v7
+; SI-NEXT: v_and_b32_e32 v6, s11, v6
+; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 2
+; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 2
+; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 2
+; SI-NEXT: v_or_b32_e32 v3, v3, v1
+; SI-NEXT: v_or_b32_e32 v2, v2, v0
+; SI-NEXT: v_or_b32_e32 v7, v7, v5
+; SI-NEXT: v_or_b32_e32 v6, v6, v4
+; SI-NEXT: v_and_b32_e32 v1, s12, v3
+; SI-NEXT: v_and_b32_e32 v0, s12, v2
+; SI-NEXT: v_and_b32_e32 v3, s13, v3
+; SI-NEXT: v_and_b32_e32 v2, s13, v2
+; SI-NEXT: v_and_b32_e32 v5, s12, v7
+; SI-NEXT: v_and_b32_e32 v4, s12, v6
+; SI-NEXT: v_and_b32_e32 v7, s13, v7
+; SI-NEXT: v_and_b32_e32 v6, s13, v6
+; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
+; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 1
+; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
+; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 1
+; SI-NEXT: v_or_b32_e32 v3, v3, v1
+; SI-NEXT: v_or_b32_e32 v2, v2, v0
+; SI-NEXT: v_or_b32_e32 v1, v7, v5
+; SI-NEXT: v_or_b32_e32 v0, v6, v4
+; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; SI-NEXT: s_endpgm
+;
+; FLAT-LABEL: v_brev_v2i64:
+; FLAT: ; %bb.0:
+; FLAT-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
+; FLAT-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
+; FLAT-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; FLAT-NEXT: v_mov_b32_e32 v8, 8
+; FLAT-NEXT: s_mov_b32 s2, 0xff0000
+; FLAT-NEXT: s_mov_b32 s3, 0xff000000
+; FLAT-NEXT: s_waitcnt lgkmcnt(0)
+; FLAT-NEXT: v_mov_b32_e32 v1, s1
+; FLAT-NEXT: v_add_u32_e32 v0, vcc, s0, v0
+; FLAT-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; FLAT-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; FLAT-NEXT: s_mov_b32 s0, 0xff00
+; FLAT-NEXT: s_mov_b32 s1, 0xf0f0f0f
+; FLAT-NEXT: s_mov_b32 s8, 0xf0f0f0f0
+; FLAT-NEXT: s_mov_b32 s9, 0x33333333
+; FLAT-NEXT: s_mov_b32 s10, 0xcccccccc
+; FLAT-NEXT: s_mov_b32 s11, 0x55555555
+; FLAT-NEXT: s_mov_b32 s12, 0xaaaaaaaa
+; FLAT-NEXT: s_mov_b32 s7, 0xf000
+; FLAT-NEXT: s_mov_b32 s6, -1
+; FLAT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; FLAT-NEXT: v_lshlrev_b64 v[4:5], 24, v[2:3]
+; FLAT-NEXT: v_lshlrev_b32_sdwa v11, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; FLAT-NEXT: v_lshlrev_b32_sdwa v14, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; FLAT-NEXT: v_lshlrev_b64 v[8:9], 8, v[0:1]
+; FLAT-NEXT: v_lshlrev_b64 v[6:7], 8, v[2:3]
+; FLAT-NEXT: v_alignbit_b32 v4, v3, v2, 24
+; FLAT-NEXT: v_alignbit_b32 v10, v3, v2, 8
+; FLAT-NEXT: v_or_b32_sdwa v3, v11, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; FLAT-NEXT: v_alignbit_b32 v12, v1, v0, 24
+; FLAT-NEXT: v_alignbit_b32 v13, v1, v0, 8
+; FLAT-NEXT: v_lshlrev_b32_e32 v8, 24, v0
+; FLAT-NEXT: v_lshlrev_b32_e32 v15, 8, v0
+; FLAT-NEXT: v_or_b32_sdwa v11, v14, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; FLAT-NEXT: v_lshlrev_b64 v[0:1], 24, v[0:1]
+; FLAT-NEXT: v_lshlrev_b32_e32 v6, 24, v2
+; FLAT-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; FLAT-NEXT: v_and_b32_e32 v0, s2, v4
+; FLAT-NEXT: v_and_b32_e32 v4, s3, v10
+; FLAT-NEXT: v_and_b32_e32 v2, s2, v2
+; FLAT-NEXT: v_or_b32_e32 v0, v4, v0
+; FLAT-NEXT: v_and_b32_e32 v1, s0, v1
+; FLAT-NEXT: v_and_b32_e32 v10, s2, v12
+; FLAT-NEXT: v_and_b32_e32 v12, s3, v13
+; FLAT-NEXT: v_and_b32_e32 v4, s0, v5
+; FLAT-NEXT: v_and_b32_e32 v13, s2, v15
+; FLAT-NEXT: v_or_b32_e32 v5, v12, v10
+; FLAT-NEXT: v_or_b32_e32 v2, v6, v2
+; FLAT-NEXT: v_or_b32_e32 v3, v0, v3
+; FLAT-NEXT: v_or_b32_sdwa v0, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; FLAT-NEXT: v_or_b32_e32 v6, v8, v13
+; FLAT-NEXT: v_or_b32_sdwa v1, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; FLAT-NEXT: v_or_b32_e32 v7, v2, v0
+; FLAT-NEXT: v_or_b32_e32 v5, v5, v11
+; FLAT-NEXT: v_or_b32_e32 v8, v6, v1
+; FLAT-NEXT: v_and_b32_e32 v0, s1, v3
+; FLAT-NEXT: v_and_b32_e32 v1, s1, v7
+; FLAT-NEXT: v_and_b32_e32 v2, s8, v3
+; FLAT-NEXT: v_and_b32_e32 v3, s8, v7
+; FLAT-NEXT: v_and_b32_e32 v4, s1, v5
+; FLAT-NEXT: v_and_b32_e32 v6, s8, v5
+; FLAT-NEXT: v_and_b32_e32 v5, s1, v8
+; FLAT-NEXT: v_and_b32_e32 v7, s8, v8
+; FLAT-NEXT: v_lshlrev_b64 v[0:1], 4, v[0:1]
+; FLAT-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3]
+; FLAT-NEXT: v_lshlrev_b64 v[4:5], 4, v[4:5]
+; FLAT-NEXT: v_lshrrev_b64 v[6:7], 4, v[6:7]
+; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
+; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
+; FLAT-NEXT: v_or_b32_e32 v7, v7, v5
+; FLAT-NEXT: v_or_b32_e32 v6, v6, v4
+; FLAT-NEXT: v_and_b32_e32 v1, s9, v3
+; FLAT-NEXT: v_and_b32_e32 v0, s9, v2
+; FLAT-NEXT: v_and_b32_e32 v5, s9, v7
+; FLAT-NEXT: v_and_b32_e32 v4, s9, v6
+; FLAT-NEXT: v_and_b32_e32 v3, s10, v3
+; FLAT-NEXT: v_and_b32_e32 v2, s10, v2
+; FLAT-NEXT: v_and_b32_e32 v7, s10, v7
+; FLAT-NEXT: v_and_b32_e32 v6, s10, v6
+; FLAT-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]
+; FLAT-NEXT: v_lshrrev_b64 v[2:3], 2, v[2:3]
+; FLAT-NEXT: v_lshlrev_b64 v[4:5], 2, v[4:5]
+; FLAT-NEXT: v_lshrrev_b64 v[6:7], 2, v[6:7]
+; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
+; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
+; FLAT-NEXT: v_or_b32_e32 v7, v7, v5
+; FLAT-NEXT: v_or_b32_e32 v6, v6, v4
+; FLAT-NEXT: v_and_b32_e32 v1, s11, v3
+; FLAT-NEXT: v_and_b32_e32 v0, s11, v2
+; FLAT-NEXT: v_and_b32_e32 v5, s11, v7
+; FLAT-NEXT: v_and_b32_e32 v4, s11, v6
+; FLAT-NEXT: v_and_b32_e32 v3, s12, v3
+; FLAT-NEXT: v_and_b32_e32 v2, s12, v2
+; FLAT-NEXT: v_and_b32_e32 v7, s12, v7
+; FLAT-NEXT: v_and_b32_e32 v6, s12, v6
+; FLAT-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; FLAT-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
+; FLAT-NEXT: v_lshlrev_b64 v[4:5], 1, v[4:5]
+; FLAT-NEXT: v_lshrrev_b64 v[6:7], 1, v[6:7]
+; FLAT-NEXT: v_or_b32_e32 v3, v3, v1
+; FLAT-NEXT: v_or_b32_e32 v2, v2, v0
+; FLAT-NEXT: v_or_b32_e32 v1, v7, v5
+; FLAT-NEXT: v_or_b32_e32 v0, v6, v4
+; FLAT-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; FLAT-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr <2 x i64> , <2 x i64> addrspace(1)* %valptr, i32 %tid
%val = load <2 x i64>, <2 x i64> addrspace(1)* %gep
@@ -113,9 +1010,21 @@ define amdgpu_kernel void @v_brev_v2i64(
ret void
}
-; FUNC-LABEL: {{^}}missing_truncate_promote_bitreverse:
-; VI: v_bfrev_b32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
define float @missing_truncate_promote_bitreverse(i32 %arg) {
+; SI-LABEL: missing_truncate_promote_bitreverse:
+; SI: ; %bb.0: ; %bb
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_bfrev_b32_e32 v0, v0
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; FLAT-LABEL: missing_truncate_promote_bitreverse:
+; FLAT: ; %bb.0: ; %bb
+; FLAT-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FLAT-NEXT: v_bfrev_b32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+; FLAT-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; FLAT-NEXT: s_setpc_b64 s[30:31]
bb:
%tmp = trunc i32 %arg to i16
%tmp1 = call i16 @llvm.bitreverse.i16(i16 %tmp)
Modified: llvm/trunk/test/CodeGen/AMDGPU/bswap.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/bswap.ll?rev=354863&r1=354862&r2=354863&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/bswap.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/bswap.ll Tue Feb 26 03:01:08 2019
@@ -1,5 +1,6 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=amdgcn-- -verify-machineinstrs | FileCheck %s --check-prefixes=FUNC,GCN,SI
+; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s -check-prefixes=FUNC,GCN,VI
declare i16 @llvm.bswap.i16(i16) nounwind readnone
declare i32 @llvm.bswap.i32(i32) nounwind readnone
@@ -10,93 +11,314 @@ declare i64 @llvm.bswap.i64(i64) nounwin
declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>) nounwind readnone
declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>) nounwind readnone
-; FUNC-LABEL: @test_bswap_i32
-; GCN: s_load_dword [[VAL:s[0-9]+]]
-; GCN-DAG: v_alignbit_b32 [[TMP0:v[0-9]+]], [[VAL]], [[VAL]], 8
-; GCN-DAG: v_alignbit_b32 [[TMP1:v[0-9]+]], [[VAL]], [[VAL]], 24
-; GCN-DAG: s_mov_b32 [[K:s[0-9]+]], 0xff00ff
-; GCN: v_bfi_b32 [[RESULT:v[0-9]+]], [[K]], [[TMP1]], [[TMP0]]
-; GCN: buffer_store_dword [[RESULT]]
-; GCN: s_endpgm
define amdgpu_kernel void @test_bswap_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
+; SI-LABEL: test_bswap_i32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_load_dword s4, s[2:3], 0x0
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, s4, s4, 8
+; SI-NEXT: v_alignbit_b32 v1, s4, s4, 24
+; SI-NEXT: s_mov_b32 s4, 0xff00ff
+; SI-NEXT: v_bfi_b32 v0, s4, v1, v0
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: test_bswap_i32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s0, s4
+; VI-NEXT: s_load_dword s4, s[6:7], 0x0
+; VI-NEXT: s_mov_b32 s1, s5
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_alignbit_b32 v0, s4, s4, 8
+; VI-NEXT: v_alignbit_b32 v1, s4, s4, 24
+; VI-NEXT: s_mov_b32 s4, 0xff00ff
+; VI-NEXT: v_bfi_b32 v0, s4, v1, v0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%val = load i32, i32 addrspace(1)* %in, align 4
%bswap = call i32 @llvm.bswap.i32(i32 %val) nounwind readnone
store i32 %bswap, i32 addrspace(1)* %out, align 4
ret void
}
-; FUNC-LABEL: @test_bswap_v2i32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_bfi_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_bfi_b32
-; GCN: s_endpgm
define amdgpu_kernel void @test_bswap_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) nounwind {
+; SI-LABEL: test_bswap_v2i32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s6, 0xff00ff
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, s5, s5, 8
+; SI-NEXT: v_alignbit_b32 v1, s5, s5, 24
+; SI-NEXT: v_alignbit_b32 v2, s4, s4, 8
+; SI-NEXT: v_alignbit_b32 v3, s4, s4, 24
+; SI-NEXT: v_bfi_b32 v1, s6, v1, v0
+; SI-NEXT: v_bfi_b32 v0, s6, v3, v2
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: test_bswap_v2i32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: s_mov_b32 s8, 0xff00ff
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s0, s4
+; VI-NEXT: s_mov_b32 s1, s5
+; VI-NEXT: s_load_dwordx2 s[4:5], s[6:7], 0x0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_alignbit_b32 v0, s5, s5, 8
+; VI-NEXT: v_alignbit_b32 v1, s5, s5, 24
+; VI-NEXT: v_alignbit_b32 v2, s4, s4, 8
+; VI-NEXT: v_alignbit_b32 v3, s4, s4, 24
+; VI-NEXT: v_bfi_b32 v1, s8, v1, v0
+; VI-NEXT: v_bfi_b32 v0, s8, v3, v2
+; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; VI-NEXT: s_endpgm
%val = load <2 x i32>, <2 x i32> addrspace(1)* %in, align 8
%bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %val) nounwind readnone
store <2 x i32> %bswap, <2 x i32> addrspace(1)* %out, align 8
ret void
}
-; FUNC-LABEL: @test_bswap_v4i32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_bfi_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_bfi_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_bfi_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_bfi_b32
-; GCN: s_endpgm
define amdgpu_kernel void @test_bswap_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) nounwind {
+; SI-LABEL: test_bswap_v4i32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s8, 0xff00ff
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, s7, s7, 8
+; SI-NEXT: v_alignbit_b32 v1, s7, s7, 24
+; SI-NEXT: v_alignbit_b32 v2, s6, s6, 8
+; SI-NEXT: v_alignbit_b32 v4, s6, s6, 24
+; SI-NEXT: v_alignbit_b32 v5, s5, s5, 8
+; SI-NEXT: v_alignbit_b32 v6, s5, s5, 24
+; SI-NEXT: v_alignbit_b32 v7, s4, s4, 8
+; SI-NEXT: v_alignbit_b32 v8, s4, s4, 24
+; SI-NEXT: v_bfi_b32 v3, s8, v1, v0
+; SI-NEXT: v_bfi_b32 v2, s8, v4, v2
+; SI-NEXT: v_bfi_b32 v1, s8, v6, v5
+; SI-NEXT: v_bfi_b32 v0, s8, v8, v7
+; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: test_bswap_v4i32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: s_mov_b32 s8, 0xff00ff
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s0, s4
+; VI-NEXT: s_mov_b32 s1, s5
+; VI-NEXT: s_load_dwordx4 s[4:7], s[6:7], 0x0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_alignbit_b32 v0, s7, s7, 8
+; VI-NEXT: v_alignbit_b32 v1, s7, s7, 24
+; VI-NEXT: v_bfi_b32 v3, s8, v1, v0
+; VI-NEXT: v_alignbit_b32 v2, s6, s6, 8
+; VI-NEXT: v_alignbit_b32 v4, s6, s6, 24
+; VI-NEXT: v_alignbit_b32 v0, s5, s5, 8
+; VI-NEXT: v_alignbit_b32 v1, s5, s5, 24
+; VI-NEXT: v_bfi_b32 v2, s8, v4, v2
+; VI-NEXT: v_bfi_b32 v1, s8, v1, v0
+; VI-NEXT: v_alignbit_b32 v0, s4, s4, 8
+; VI-NEXT: v_alignbit_b32 v4, s4, s4, 24
+; VI-NEXT: v_bfi_b32 v0, s8, v4, v0
+; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; VI-NEXT: s_endpgm
%val = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16
%bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val) nounwind readnone
store <4 x i32> %bswap, <4 x i32> addrspace(1)* %out, align 16
ret void
}
-; FUNC-LABEL: @test_bswap_v8i32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_bfi_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_bfi_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_bfi_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_bfi_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_bfi_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_bfi_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_bfi_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_alignbit_b32
-; GCN-DAG: v_bfi_b32
-; GCN: s_endpgm
define amdgpu_kernel void @test_bswap_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) nounwind {
+; SI-LABEL: test_bswap_v8i32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; SI-NEXT: s_mov_b32 s11, 0xf000
+; SI-NEXT: s_mov_b32 s10, -1
+; SI-NEXT: s_mov_b32 s12, 0xff00ff
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_alignbit_b32 v0, s3, s3, 8
+; SI-NEXT: v_alignbit_b32 v1, s3, s3, 24
+; SI-NEXT: v_alignbit_b32 v2, s2, s2, 8
+; SI-NEXT: v_alignbit_b32 v4, s2, s2, 24
+; SI-NEXT: v_alignbit_b32 v5, s1, s1, 8
+; SI-NEXT: v_alignbit_b32 v6, s1, s1, 24
+; SI-NEXT: v_alignbit_b32 v7, s0, s0, 8
+; SI-NEXT: v_alignbit_b32 v8, s0, s0, 24
+; SI-NEXT: v_alignbit_b32 v9, s7, s7, 8
+; SI-NEXT: v_alignbit_b32 v10, s7, s7, 24
+; SI-NEXT: v_alignbit_b32 v11, s6, s6, 8
+; SI-NEXT: v_alignbit_b32 v12, s6, s6, 24
+; SI-NEXT: v_alignbit_b32 v13, s5, s5, 8
+; SI-NEXT: v_alignbit_b32 v14, s5, s5, 24
+; SI-NEXT: v_alignbit_b32 v15, s4, s4, 8
+; SI-NEXT: v_alignbit_b32 v16, s4, s4, 24
+; SI-NEXT: v_bfi_b32 v3, s12, v1, v0
+; SI-NEXT: v_bfi_b32 v2, s12, v4, v2
+; SI-NEXT: v_bfi_b32 v1, s12, v6, v5
+; SI-NEXT: v_bfi_b32 v0, s12, v8, v7
+; SI-NEXT: v_bfi_b32 v7, s12, v10, v9
+; SI-NEXT: v_bfi_b32 v6, s12, v12, v11
+; SI-NEXT: v_bfi_b32 v5, s12, v14, v13
+; SI-NEXT: v_bfi_b32 v4, s12, v16, v15
+; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16
+; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: test_bswap_v8i32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; VI-NEXT: s_mov_b32 s12, 0xff00ff
+; VI-NEXT: s_mov_b32 s11, 0xf000
+; VI-NEXT: s_mov_b32 s10, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s8, s0
+; VI-NEXT: s_mov_b32 s9, s1
+; VI-NEXT: s_load_dwordx8 s[0:7], s[2:3], 0x0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_alignbit_b32 v0, s3, s3, 8
+; VI-NEXT: v_alignbit_b32 v1, s3, s3, 24
+; VI-NEXT: v_bfi_b32 v3, s12, v1, v0
+; VI-NEXT: v_alignbit_b32 v2, s2, s2, 8
+; VI-NEXT: v_alignbit_b32 v4, s2, s2, 24
+; VI-NEXT: v_alignbit_b32 v0, s1, s1, 8
+; VI-NEXT: v_alignbit_b32 v1, s1, s1, 24
+; VI-NEXT: v_bfi_b32 v2, s12, v4, v2
+; VI-NEXT: v_bfi_b32 v1, s12, v1, v0
+; VI-NEXT: v_alignbit_b32 v0, s0, s0, 8
+; VI-NEXT: v_alignbit_b32 v4, s0, s0, 24
+; VI-NEXT: v_bfi_b32 v0, s12, v4, v0
+; VI-NEXT: v_alignbit_b32 v4, s7, s7, 8
+; VI-NEXT: v_alignbit_b32 v5, s7, s7, 24
+; VI-NEXT: v_bfi_b32 v7, s12, v5, v4
+; VI-NEXT: v_alignbit_b32 v4, s6, s6, 8
+; VI-NEXT: v_alignbit_b32 v5, s6, s6, 24
+; VI-NEXT: v_bfi_b32 v6, s12, v5, v4
+; VI-NEXT: v_alignbit_b32 v4, s5, s5, 8
+; VI-NEXT: v_alignbit_b32 v5, s5, s5, 24
+; VI-NEXT: v_bfi_b32 v5, s12, v5, v4
+; VI-NEXT: v_alignbit_b32 v4, s4, s4, 8
+; VI-NEXT: v_alignbit_b32 v8, s4, s4, 24
+; VI-NEXT: v_bfi_b32 v4, s12, v8, v4
+; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16
+; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; VI-NEXT: s_endpgm
%val = load <8 x i32>, <8 x i32> addrspace(1)* %in, align 32
%bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %val) nounwind readnone
store <8 x i32> %bswap, <8 x i32> addrspace(1)* %out, align 32
ret void
}
-; FUNC-LABEL: {{^}}test_bswap_i64:
-; GCN-NOT: v_or_b32_e64 v{{[0-9]+}}, 0, 0
define amdgpu_kernel void @test_bswap_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
+; SI-LABEL: test_bswap_i64:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_mov_b32 s19, 0xff0000
+; SI-NEXT: s_mov_b32 s9, 0
+; SI-NEXT: s_mov_b32 s15, 0xff00
+; SI-NEXT: s_mov_b32 s11, s9
+; SI-NEXT: s_mov_b32 s12, s9
+; SI-NEXT: s_mov_b32 s14, s9
+; SI-NEXT: s_mov_b32 s16, s9
+; SI-NEXT: s_mov_b32 s18, s9
+; SI-NEXT: s_mov_b32 s4, s0
+; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s2
+; SI-NEXT: v_alignbit_b32 v1, s3, v0, 24
+; SI-NEXT: v_alignbit_b32 v0, s3, v0, 8
+; SI-NEXT: s_lshr_b32 s8, s3, 24
+; SI-NEXT: s_lshr_b32 s10, s3, 8
+; SI-NEXT: s_lshl_b64 s[0:1], s[2:3], 8
+; SI-NEXT: s_lshl_b64 s[20:21], s[2:3], 24
+; SI-NEXT: s_lshl_b32 s17, s2, 24
+; SI-NEXT: s_lshl_b32 s0, s2, 8
+; SI-NEXT: v_and_b32_e32 v1, s19, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xff000000, v0
+; SI-NEXT: s_and_b32 s10, s10, s15
+; SI-NEXT: s_and_b32 s13, s1, 0xff
+; SI-NEXT: s_and_b32 s15, s21, s15
+; SI-NEXT: s_and_b32 s19, s0, s19
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: s_or_b64 s[0:1], s[10:11], s[8:9]
+; SI-NEXT: s_or_b64 s[2:3], s[14:15], s[12:13]
+; SI-NEXT: s_or_b64 s[8:9], s[16:17], s[18:19]
+; SI-NEXT: v_or_b32_e32 v0, s0, v0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: s_or_b64 s[0:1], s[8:9], s[2:3]
+; SI-NEXT: v_or_b32_e32 v0, s0, v0
+; SI-NEXT: v_or_b32_e32 v1, s1, v1
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: test_bswap_i64:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: s_mov_b32 s12, 0xff0000
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0
+; VI-NEXT: s_mov_b32 s1, s5
+; VI-NEXT: s_mov_b32 s5, 0
+; VI-NEXT: s_mov_b32 s0, s4
+; VI-NEXT: s_mov_b32 s9, s5
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s6
+; VI-NEXT: v_alignbit_b32 v1, s7, v0, 24
+; VI-NEXT: v_alignbit_b32 v0, s7, v0, 8
+; VI-NEXT: s_bfe_u32 s8, s7, 0x80010
+; VI-NEXT: v_and_b32_e32 v1, s12, v1
+; VI-NEXT: v_and_b32_e32 v0, 0xff000000, v0
+; VI-NEXT: s_lshr_b32 s4, s7, 24
+; VI-NEXT: s_lshl_b32 s8, s8, 8
+; VI-NEXT: s_or_b64 s[8:9], s[8:9], s[4:5]
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: s_lshl_b64 s[10:11], s[6:7], 24
+; VI-NEXT: v_or_b32_e32 v0, s8, v0
+; VI-NEXT: v_mov_b32_e32 v1, s9
+; VI-NEXT: s_lshl_b64 s[8:9], s[6:7], 8
+; VI-NEXT: s_lshl_b32 s4, s6, 8
+; VI-NEXT: s_and_b32 s9, s9, 0xff
+; VI-NEXT: s_mov_b32 s8, s5
+; VI-NEXT: s_and_b32 s11, s11, 0xff00
+; VI-NEXT: s_mov_b32 s10, s5
+; VI-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
+; VI-NEXT: s_lshl_b32 s11, s6, 24
+; VI-NEXT: s_and_b32 s7, s4, s12
+; VI-NEXT: s_mov_b32 s6, s5
+; VI-NEXT: s_or_b64 s[4:5], s[10:11], s[6:7]
+; VI-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
+; VI-NEXT: v_or_b32_e32 v0, s4, v0
+; VI-NEXT: v_or_b32_e32 v1, s5, v1
+; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; VI-NEXT: s_endpgm
%val = load i64, i64 addrspace(1)* %in, align 8
%bswap = call i64 @llvm.bswap.i64(i64 %val) nounwind readnone
store i64 %bswap, i64 addrspace(1)* %out, align 8
@@ -104,6 +326,155 @@ define amdgpu_kernel void @test_bswap_i6
}
define amdgpu_kernel void @test_bswap_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) nounwind {
+; SI-LABEL: test_bswap_v2i64:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s31, 0xff0000
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_load_dwordx4 s[8:11], s[6:7], 0x0
+; SI-NEXT: s_mov_b32 s7, 0
+; SI-NEXT: s_mov_b32 s22, 0xff000000
+; SI-NEXT: s_mov_b32 s27, 0xff00
+; SI-NEXT: s_movk_i32 s25, 0xff
+; SI-NEXT: s_mov_b32 s13, s7
+; SI-NEXT: s_mov_b32 s14, s7
+; SI-NEXT: s_mov_b32 s16, s7
+; SI-NEXT: s_mov_b32 s18, s7
+; SI-NEXT: s_mov_b32 s20, s7
+; SI-NEXT: s_mov_b32 s23, s7
+; SI-NEXT: s_mov_b32 s24, s7
+; SI-NEXT: s_mov_b32 s26, s7
+; SI-NEXT: s_mov_b32 s28, s7
+; SI-NEXT: s_mov_b32 s30, s7
+; SI-NEXT: s_mov_b32 s0, s4
+; SI-NEXT: s_mov_b32 s1, s5
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s10
+; SI-NEXT: v_alignbit_b32 v1, s11, v0, 24
+; SI-NEXT: v_alignbit_b32 v0, s11, v0, 8
+; SI-NEXT: s_lshr_b32 s6, s11, 24
+; SI-NEXT: s_lshr_b32 s12, s11, 8
+; SI-NEXT: s_lshl_b64 s[4:5], s[10:11], 8
+; SI-NEXT: s_lshl_b64 s[32:33], s[10:11], 24
+; SI-NEXT: s_lshl_b32 s19, s10, 24
+; SI-NEXT: s_lshl_b32 s21, s10, 8
+; SI-NEXT: v_mov_b32_e32 v2, s8
+; SI-NEXT: v_alignbit_b32 v3, s9, v2, 24
+; SI-NEXT: v_alignbit_b32 v2, s9, v2, 8
+; SI-NEXT: s_lshr_b32 s32, s9, 8
+; SI-NEXT: s_lshl_b64 s[10:11], s[8:9], 8
+; SI-NEXT: s_and_b32 s15, s5, s25
+; SI-NEXT: s_lshl_b64 s[4:5], s[8:9], 24
+; SI-NEXT: s_lshl_b32 s29, s8, 24
+; SI-NEXT: s_lshl_b32 s4, s8, 8
+; SI-NEXT: v_and_b32_e32 v1, s31, v1
+; SI-NEXT: v_and_b32_e32 v0, s22, v0
+; SI-NEXT: s_and_b32 s12, s12, s27
+; SI-NEXT: s_and_b32 s17, s33, s27
+; SI-NEXT: s_and_b32 s21, s21, s31
+; SI-NEXT: v_and_b32_e32 v3, s31, v3
+; SI-NEXT: v_and_b32_e32 v2, s22, v2
+; SI-NEXT: s_and_b32 s22, s32, s27
+; SI-NEXT: s_and_b32 s25, s11, s25
+; SI-NEXT: s_and_b32 s27, s5, s27
+; SI-NEXT: s_and_b32 s31, s4, s31
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: s_or_b64 s[4:5], s[12:13], s[6:7]
+; SI-NEXT: s_or_b64 s[10:11], s[16:17], s[14:15]
+; SI-NEXT: s_or_b64 s[12:13], s[18:19], s[20:21]
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
+; SI-NEXT: s_lshr_b32 s6, s9, 24
+; SI-NEXT: s_or_b64 s[8:9], s[26:27], s[24:25]
+; SI-NEXT: s_or_b64 s[14:15], s[28:29], s[30:31]
+; SI-NEXT: v_or_b32_e32 v0, s4, v0
+; SI-NEXT: v_mov_b32_e32 v3, s5
+; SI-NEXT: s_or_b64 s[4:5], s[12:13], s[10:11]
+; SI-NEXT: s_or_b64 s[6:7], s[22:23], s[6:7]
+; SI-NEXT: s_or_b64 s[8:9], s[14:15], s[8:9]
+; SI-NEXT: v_or_b32_e32 v2, s4, v0
+; SI-NEXT: v_or_b32_e32 v3, s5, v3
+; SI-NEXT: v_or_b32_e32 v0, s6, v1
+; SI-NEXT: v_mov_b32_e32 v1, s7
+; SI-NEXT: v_or_b32_e32 v0, s8, v0
+; SI-NEXT: v_or_b32_e32 v1, s9, v1
+; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: test_bswap_v2i64:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: s_mov_b32 s9, 0
+; VI-NEXT: s_mov_b32 s14, 0xff0000
+; VI-NEXT: s_mov_b32 s15, 0xff000000
+; VI-NEXT: s_mov_b32 s11, s9
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s0, s4
+; VI-NEXT: s_mov_b32 s1, s5
+; VI-NEXT: s_load_dwordx4 s[4:7], s[6:7], 0x0
+; VI-NEXT: s_movk_i32 s16, 0xff
+; VI-NEXT: s_mov_b32 s17, 0xff00
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s6
+; VI-NEXT: v_alignbit_b32 v1, s7, v0, 24
+; VI-NEXT: v_alignbit_b32 v0, s7, v0, 8
+; VI-NEXT: s_bfe_u32 s10, s7, 0x80010
+; VI-NEXT: v_and_b32_e32 v1, s14, v1
+; VI-NEXT: v_and_b32_e32 v0, s15, v0
+; VI-NEXT: s_lshr_b32 s8, s7, 24
+; VI-NEXT: s_lshl_b32 s10, s10, 8
+; VI-NEXT: s_or_b64 s[10:11], s[10:11], s[8:9]
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 24
+; VI-NEXT: v_or_b32_e32 v0, s10, v0
+; VI-NEXT: v_mov_b32_e32 v1, s11
+; VI-NEXT: s_lshl_b64 s[10:11], s[6:7], 8
+; VI-NEXT: s_and_b32 s11, s11, s16
+; VI-NEXT: s_mov_b32 s10, s9
+; VI-NEXT: s_and_b32 s13, s13, s17
+; VI-NEXT: s_mov_b32 s12, s9
+; VI-NEXT: s_or_b64 s[10:11], s[12:13], s[10:11]
+; VI-NEXT: s_lshl_b32 s13, s6, 24
+; VI-NEXT: s_lshl_b32 s6, s6, 8
+; VI-NEXT: s_and_b32 s7, s6, s14
+; VI-NEXT: s_mov_b32 s6, s9
+; VI-NEXT: s_or_b64 s[6:7], s[12:13], s[6:7]
+; VI-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
+; VI-NEXT: v_or_b32_e32 v2, s6, v0
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: v_or_b32_e32 v3, s7, v1
+; VI-NEXT: v_alignbit_b32 v1, s5, v0, 24
+; VI-NEXT: v_alignbit_b32 v0, s5, v0, 8
+; VI-NEXT: s_bfe_u32 s6, s5, 0x80010
+; VI-NEXT: v_and_b32_e32 v1, s14, v1
+; VI-NEXT: v_and_b32_e32 v0, s15, v0
+; VI-NEXT: s_lshr_b32 s8, s5, 24
+; VI-NEXT: s_lshl_b32 s6, s6, 8
+; VI-NEXT: s_mov_b32 s7, s9
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
+; VI-NEXT: s_lshl_b64 s[10:11], s[4:5], 24
+; VI-NEXT: v_or_b32_e32 v0, s6, v0
+; VI-NEXT: v_mov_b32_e32 v1, s7
+; VI-NEXT: s_lshl_b64 s[6:7], s[4:5], 8
+; VI-NEXT: s_and_b32 s7, s7, s16
+; VI-NEXT: s_mov_b32 s6, s9
+; VI-NEXT: s_and_b32 s11, s11, s17
+; VI-NEXT: s_mov_b32 s10, s9
+; VI-NEXT: s_or_b64 s[6:7], s[10:11], s[6:7]
+; VI-NEXT: s_lshl_b32 s11, s4, 24
+; VI-NEXT: s_lshl_b32 s4, s4, 8
+; VI-NEXT: s_and_b32 s5, s4, s14
+; VI-NEXT: s_mov_b32 s4, s9
+; VI-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5]
+; VI-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
+; VI-NEXT: v_or_b32_e32 v0, s4, v0
+; VI-NEXT: v_or_b32_e32 v1, s5, v1
+; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; VI-NEXT: s_endpgm
%val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16
%bswap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %val) nounwind readnone
store <2 x i64> %bswap, <2 x i64> addrspace(1)* %out, align 16
@@ -111,18 +482,263 @@ define amdgpu_kernel void @test_bswap_v2
}
define amdgpu_kernel void @test_bswap_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) nounwind {
+; SI-LABEL: test_bswap_v4i64:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s31, 0xff0000
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_load_dwordx8 s[4:11], s[14:15], 0x0
+; SI-NEXT: s_mov_b32 s27, 0xff000000
+; SI-NEXT: s_mov_b32 s34, 0xff00
+; SI-NEXT: s_mov_b32 s14, 0
+; SI-NEXT: s_movk_i32 s36, 0xff
+; SI-NEXT: s_mov_b32 s16, s14
+; SI-NEXT: s_mov_b32 s18, s14
+; SI-NEXT: s_mov_b32 s20, s14
+; SI-NEXT: s_mov_b32 s22, s14
+; SI-NEXT: s_mov_b32 s24, s14
+; SI-NEXT: s_mov_b32 s26, s14
+; SI-NEXT: s_mov_b32 s28, s14
+; SI-NEXT: s_mov_b32 s30, s14
+; SI-NEXT: s_mov_b32 s0, s12
+; SI-NEXT: s_mov_b32 s1, s13
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_mov_b32_e32 v0, s6
+; SI-NEXT: v_alignbit_b32 v1, s7, v0, 24
+; SI-NEXT: v_alignbit_b32 v0, s7, v0, 8
+; SI-NEXT: s_lshr_b32 s35, s7, 24
+; SI-NEXT: s_lshr_b32 s37, s7, 8
+; SI-NEXT: v_mov_b32_e32 v2, s4
+; SI-NEXT: v_alignbit_b32 v3, s5, v2, 24
+; SI-NEXT: v_alignbit_b32 v2, s5, v2, 8
+; SI-NEXT: s_lshr_b32 s38, s5, 24
+; SI-NEXT: s_lshr_b32 s39, s5, 8
+; SI-NEXT: s_lshl_b64 s[12:13], s[6:7], 8
+; SI-NEXT: s_lshl_b64 s[32:33], s[6:7], 24
+; SI-NEXT: s_lshl_b32 s7, s6, 8
+; SI-NEXT: s_and_b32 s15, s13, s36
+; SI-NEXT: s_lshl_b64 s[12:13], s[4:5], 8
+; SI-NEXT: s_and_b32 s17, s33, s34
+; SI-NEXT: s_lshl_b64 s[32:33], s[4:5], 24
+; SI-NEXT: s_lshl_b32 s5, s4, 8
+; SI-NEXT: v_mov_b32_e32 v4, s10
+; SI-NEXT: v_alignbit_b32 v5, s11, v4, 24
+; SI-NEXT: v_alignbit_b32 v4, s11, v4, 8
+; SI-NEXT: s_and_b32 s21, s33, s34
+; SI-NEXT: s_lshl_b64 s[32:33], s[10:11], 24
+; SI-NEXT: s_and_b32 s25, s33, s34
+; SI-NEXT: s_lshl_b64 s[32:33], s[8:9], 24
+; SI-NEXT: s_and_b32 s29, s33, s34
+; SI-NEXT: s_lshr_b32 s12, s11, 24
+; SI-NEXT: s_lshr_b32 s40, s11, 8
+; SI-NEXT: v_mov_b32_e32 v6, s8
+; SI-NEXT: v_alignbit_b32 v7, s9, v6, 24
+; SI-NEXT: v_alignbit_b32 v6, s9, v6, 8
+; SI-NEXT: s_and_b32 s19, s7, s31
+; SI-NEXT: s_lshr_b32 s7, s9, 24
+; SI-NEXT: s_and_b32 s23, s5, s31
+; SI-NEXT: s_lshr_b32 s5, s9, 8
+; SI-NEXT: v_and_b32_e32 v0, s27, v0
+; SI-NEXT: v_and_b32_e32 v2, s27, v2
+; SI-NEXT: v_and_b32_e32 v4, s27, v4
+; SI-NEXT: v_and_b32_e32 v6, s27, v6
+; SI-NEXT: s_lshl_b32 s27, s10, 8
+; SI-NEXT: s_and_b32 s27, s27, s31
+; SI-NEXT: s_lshl_b32 s32, s8, 8
+; SI-NEXT: v_and_b32_e32 v1, s31, v1
+; SI-NEXT: v_and_b32_e32 v3, s31, v3
+; SI-NEXT: v_and_b32_e32 v5, s31, v5
+; SI-NEXT: v_and_b32_e32 v7, s31, v7
+; SI-NEXT: s_and_b32 s31, s32, s31
+; SI-NEXT: s_lshl_b64 s[32:33], s[10:11], 8
+; SI-NEXT: s_and_b32 s11, s37, s34
+; SI-NEXT: s_and_b32 s32, s39, s34
+; SI-NEXT: s_and_b32 s37, s40, s34
+; SI-NEXT: s_and_b32 s5, s5, s34
+; SI-NEXT: s_or_b32 s11, s11, s35
+; SI-NEXT: s_lshl_b64 s[34:35], s[8:9], 8
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: v_or_b32_e32 v1, v2, v3
+; SI-NEXT: s_or_b32 s9, s32, s38
+; SI-NEXT: s_or_b64 s[16:17], s[16:17], s[14:15]
+; SI-NEXT: s_lshl_b32 s15, s6, 24
+; SI-NEXT: v_or_b32_e32 v3, v4, v5
+; SI-NEXT: s_or_b32 s12, s37, s12
+; SI-NEXT: v_or_b32_e32 v4, v6, v7
+; SI-NEXT: s_or_b32 s32, s5, s7
+; SI-NEXT: v_or_b32_e32 v2, s11, v0
+; SI-NEXT: v_or_b32_e32 v0, s9, v1
+; SI-NEXT: s_or_b64 s[6:7], s[14:15], s[18:19]
+; SI-NEXT: s_and_b32 s15, s13, s36
+; SI-NEXT: v_or_b32_e32 v6, s12, v3
+; SI-NEXT: s_or_b64 s[6:7], s[6:7], s[16:17]
+; SI-NEXT: s_or_b64 s[12:13], s[20:21], s[14:15]
+; SI-NEXT: s_lshl_b32 s15, s4, 24
+; SI-NEXT: s_or_b64 s[4:5], s[14:15], s[22:23]
+; SI-NEXT: s_and_b32 s15, s33, s36
+; SI-NEXT: s_or_b64 s[4:5], s[4:5], s[12:13]
+; SI-NEXT: s_or_b64 s[12:13], s[24:25], s[14:15]
+; SI-NEXT: s_lshl_b32 s15, s10, 24
+; SI-NEXT: s_or_b64 s[10:11], s[14:15], s[26:27]
+; SI-NEXT: s_and_b32 s15, s35, s36
+; SI-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
+; SI-NEXT: s_or_b64 s[12:13], s[28:29], s[14:15]
+; SI-NEXT: s_lshl_b32 s15, s8, 24
+; SI-NEXT: s_or_b64 s[8:9], s[14:15], s[30:31]
+; SI-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13]
+; SI-NEXT: v_or_b32_e32 v4, s32, v4
+; SI-NEXT: v_mov_b32_e32 v3, s7
+; SI-NEXT: v_mov_b32_e32 v1, s5
+; SI-NEXT: v_mov_b32_e32 v7, s11
+; SI-NEXT: v_mov_b32_e32 v5, s9
+; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: test_bswap_v4i64:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: s_mov_b32 s16, 0xff0000
+; VI-NEXT: s_mov_b32 s17, 0xff000000
+; VI-NEXT: s_movk_i32 s18, 0xff
+; VI-NEXT: s_mov_b32 s19, 0xff00
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s0, s4
+; VI-NEXT: s_mov_b32 s1, s5
+; VI-NEXT: s_load_dwordx8 s[4:11], s[6:7], 0x0
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s6
+; VI-NEXT: v_alignbit_b32 v1, s7, v0, 24
+; VI-NEXT: v_alignbit_b32 v0, s7, v0, 8
+; VI-NEXT: s_bfe_u32 s13, s7, 0x80010
+; VI-NEXT: v_and_b32_e32 v1, s16, v1
+; VI-NEXT: v_and_b32_e32 v0, s17, v0
+; VI-NEXT: s_lshr_b32 s12, s7, 24
+; VI-NEXT: s_lshl_b32 s13, s13, 8
+; VI-NEXT: s_or_b32 s12, s13, s12
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v2, s12, v0
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: v_alignbit_b32 v1, s5, v0, 24
+; VI-NEXT: v_alignbit_b32 v0, s5, v0, 8
+; VI-NEXT: s_bfe_u32 s13, s5, 0x80010
+; VI-NEXT: v_and_b32_e32 v1, s16, v1
+; VI-NEXT: v_and_b32_e32 v0, s17, v0
+; VI-NEXT: s_lshr_b32 s12, s5, 24
+; VI-NEXT: s_lshl_b32 s13, s13, 8
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: s_or_b32 s12, s13, s12
+; VI-NEXT: v_or_b32_e32 v0, s12, v0
+; VI-NEXT: s_lshl_b64 s[12:13], s[6:7], 8
+; VI-NEXT: s_lshl_b64 s[14:15], s[6:7], 24
+; VI-NEXT: s_mov_b32 s12, 0
+; VI-NEXT: s_and_b32 s13, s13, s18
+; VI-NEXT: s_and_b32 s15, s15, s19
+; VI-NEXT: s_mov_b32 s14, s12
+; VI-NEXT: s_or_b64 s[14:15], s[14:15], s[12:13]
+; VI-NEXT: s_lshl_b32 s13, s6, 24
+; VI-NEXT: s_lshl_b32 s6, s6, 8
+; VI-NEXT: s_and_b32 s7, s6, s16
+; VI-NEXT: s_mov_b32 s6, s12
+; VI-NEXT: s_or_b64 s[6:7], s[12:13], s[6:7]
+; VI-NEXT: s_or_b64 s[6:7], s[6:7], s[14:15]
+; VI-NEXT: s_lshl_b64 s[14:15], s[4:5], 8
+; VI-NEXT: s_and_b32 s13, s15, s18
+; VI-NEXT: s_lshl_b64 s[14:15], s[4:5], 24
+; VI-NEXT: s_and_b32 s15, s15, s19
+; VI-NEXT: s_mov_b32 s14, s12
+; VI-NEXT: s_or_b64 s[14:15], s[14:15], s[12:13]
+; VI-NEXT: s_lshl_b32 s13, s4, 24
+; VI-NEXT: s_lshl_b32 s4, s4, 8
+; VI-NEXT: s_and_b32 s5, s4, s16
+; VI-NEXT: s_mov_b32 s4, s12
+; VI-NEXT: s_or_b64 s[4:5], s[12:13], s[4:5]
+; VI-NEXT: v_mov_b32_e32 v1, s10
+; VI-NEXT: v_alignbit_b32 v3, s11, v1, 24
+; VI-NEXT: s_or_b64 s[4:5], s[4:5], s[14:15]
+; VI-NEXT: v_alignbit_b32 v1, s11, v1, 8
+; VI-NEXT: s_bfe_u32 s6, s11, 0x80010
+; VI-NEXT: v_and_b32_e32 v3, s16, v3
+; VI-NEXT: v_and_b32_e32 v1, s17, v1
+; VI-NEXT: s_lshr_b32 s4, s11, 24
+; VI-NEXT: s_lshl_b32 s6, s6, 8
+; VI-NEXT: s_or_b32 s4, s6, s4
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_or_b32_e32 v5, s4, v1
+; VI-NEXT: v_mov_b32_e32 v1, s8
+; VI-NEXT: v_alignbit_b32 v3, s9, v1, 24
+; VI-NEXT: v_alignbit_b32 v1, s9, v1, 8
+; VI-NEXT: s_bfe_u32 s6, s9, 0x80010
+; VI-NEXT: s_lshl_b64 s[14:15], s[10:11], 8
+; VI-NEXT: v_and_b32_e32 v3, s16, v3
+; VI-NEXT: v_and_b32_e32 v1, s17, v1
+; VI-NEXT: s_lshr_b32 s4, s9, 24
+; VI-NEXT: s_lshl_b32 s6, s6, 8
+; VI-NEXT: s_and_b32 s13, s15, s18
+; VI-NEXT: s_lshl_b64 s[14:15], s[10:11], 24
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: s_or_b32 s4, s6, s4
+; VI-NEXT: v_or_b32_e32 v3, s4, v1
+; VI-NEXT: s_lshl_b32 s4, s10, 8
+; VI-NEXT: s_and_b32 s15, s15, s19
+; VI-NEXT: s_mov_b32 s14, s12
+; VI-NEXT: s_or_b64 s[14:15], s[14:15], s[12:13]
+; VI-NEXT: s_lshl_b32 s13, s10, 24
+; VI-NEXT: s_and_b32 s11, s4, s16
+; VI-NEXT: s_mov_b32 s10, s12
+; VI-NEXT: s_or_b64 s[10:11], s[12:13], s[10:11]
+; VI-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15]
+; VI-NEXT: s_lshl_b64 s[14:15], s[8:9], 8
+; VI-NEXT: s_and_b32 s13, s15, s18
+; VI-NEXT: s_lshl_b64 s[14:15], s[8:9], 24
+; VI-NEXT: s_lshl_b32 s4, s8, 8
+; VI-NEXT: s_and_b32 s15, s15, s19
+; VI-NEXT: s_mov_b32 s14, s12
+; VI-NEXT: s_or_b64 s[14:15], s[14:15], s[12:13]
+; VI-NEXT: s_lshl_b32 s13, s8, 24
+; VI-NEXT: s_and_b32 s9, s4, s16
+; VI-NEXT: s_mov_b32 s8, s12
+; VI-NEXT: s_or_b64 s[8:9], s[12:13], s[8:9]
+; VI-NEXT: s_or_b64 s[8:9], s[8:9], s[14:15]
+; VI-NEXT: v_mov_b32_e32 v4, s9
+; VI-NEXT: v_mov_b32_e32 v6, s11
+; VI-NEXT: buffer_store_dwordx4 v[3:6], off, s[0:3], 0 offset:16
+; VI-NEXT: v_mov_b32_e32 v1, s5
+; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; VI-NEXT: s_endpgm
%val = load <4 x i64>, <4 x i64> addrspace(1)* %in, align 32
%bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %val) nounwind readnone
store <4 x i64> %bswap, <4 x i64> addrspace(1)* %out, align 32
ret void
}
-; GCN-LABEL: {{^}}missing_truncate_promote_bswap:
-; VI: v_and_b32
-; VI: v_alignbit_b32
-; VI: v_alignbit_b32
-; VI: v_bfi_b32
define float @missing_truncate_promote_bswap(i32 %arg) {
+; SI-LABEL: missing_truncate_promote_bswap:
+; SI: ; %bb.0: ; %bb
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_alignbit_b32 v1, v0, v0, 8
+; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24
+; SI-NEXT: s_mov_b32 s6, 0xff00ff
+; SI-NEXT: v_bfi_b32 v0, s6, v0, v1
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: missing_truncate_promote_bswap:
+; VI: ; %bb.0: ; %bb
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; VI-NEXT: v_alignbit_b32 v1, v0, v0, 8
+; VI-NEXT: v_alignbit_b32 v0, v0, v0, 24
+; VI-NEXT: s_mov_b32 s6, 0xff00ff
+; VI-NEXT: v_bfi_b32 v0, s6, v0, v1
+; VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; VI-NEXT: s_setpc_b64 s[30:31]
bb:
%tmp = trunc i32 %arg to i16
%tmp1 = call i16 @llvm.bswap.i16(i16 %tmp)
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