[PATCH] D58632: [X86] Improve lowering of idemptotent RMW operations

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
reames added a reviewer: jfb.
Herald added subscribers: jdoerfert, bollu, mcrosier.

The current lowering uses an mfence.  mfences are substaintially higher latency than the locked operations originally requested, but we do want to avoid contention on the original cache line.  As such, use a locked instruction on a cache line assumed to be thread local.


https://reviews.llvm.org/D58632

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/atomic-idempotent.ll

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