[llvm] r354640 - [X86] Fix some copy/paste mistakes that caused a VR128 to be used as the address of a load in an isel pattern

[Craig Topper via llvm-commits]

Author: ctopper
Date: Thu Feb 21 16:04:35 2019
New Revision: 354640

URL: http://llvm.org/viewvc/llvm-project?rev=354640&view=rev
Log:
[X86] Fix some copy/paste mistakes that caused a VR128 to be used as the address of a load in an isel pattern

This was introduced in r354511.

Fixes PR40811.

Added:
    llvm/trunk/test/CodeGen/X86/pr40811.ll
Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=354640&r1=354639&r2=354640&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Feb 21 16:04:35 2019
@@ -6535,9 +6535,9 @@ def : Pat<(X86Blendi (loadv8i32 addr:$sr
 
 def : Pat<(X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2), imm:$src3),
           (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$src3)>;
-def : Pat<(X86Blendi VR128:$src1, (loadv4i32 VR128:$src2), imm:$src3),
+def : Pat<(X86Blendi VR128:$src1, (loadv4i32 addr:$src2), imm:$src3),
           (VBLENDPSrmi VR128:$src1, addr:$src2, imm:$src3)>;
-def : Pat<(X86Blendi (loadv4i32 VR128:$src2), VR128:$src1, imm:$src3),
+def : Pat<(X86Blendi (loadv4i32 addr:$src2), VR128:$src1, imm:$src3),
           (VBLENDPSrmi VR128:$src1, addr:$src2, (BlendCommuteImm4 imm:$src3))>;
 }
 
@@ -6562,9 +6562,9 @@ def : Pat<(X86Blendi (memopv2i64 addr:$s
 def : Pat<(X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2), imm:$src3),
           (BLENDPSrri VR128:$src1, VR128:$src2, imm:$src3)>;
 def : Pat<(X86Blendi VR128:$src1, (memopv4i32 addr:$src2), imm:$src3),
-          (BLENDPSrmi VR128:$src1,addr:$src2, imm:$src3)>;
+          (BLENDPSrmi VR128:$src1, addr:$src2, imm:$src3)>;
 def : Pat<(X86Blendi (memopv4i32 addr:$src2), VR128:$src1, imm:$src3),
-          (BLENDPSrmi VR128:$src1,addr:$src2, (BlendCommuteImm4 imm:$src3))>;
+          (BLENDPSrmi VR128:$src1, addr:$src2, (BlendCommuteImm4 imm:$src3))>;
 }
 
 // For insertion into the zero index (low half) of a 256-bit vector, it is

Added: llvm/trunk/test/CodeGen/X86/pr40811.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr40811.ll?rev=354640&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr40811.ll (added)
+++ llvm/trunk/test/CodeGen/X86/pr40811.ll Thu Feb 21 16:04:35 2019
@@ -0,0 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -o - -mcpu=btver2 -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
+
+define <8 x i32> @_Z6test70v(<4 x i32>* %id14793) {
+; CHECK-LABEL: _Z6test70v:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmovaps (%rdi), %xmm0
+; CHECK-NEXT:    vblendps {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2,3]
+; CHECK-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[1,3,1,0]
+; CHECK-NEXT:    vpermilps {{.*#+}} xmm1 = xmm1[0,2,1,0]
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT:    retq
+entry:
+  %id14793.0.id14793.0. = load <4 x i32>, <4 x i32>* %id14793, align 16
+  %shuffle = shufflevector <4 x i32> %id14793.0.id14793.0., <4 x i32> <i32 undef, i32 -1052558824, i32 undef, i32 undef>, <8 x i32> <i32 0, i32 2, i32 5, i32 0, i32 1, i32 3, i32 1, i32 0>
+  ret <8 x i32> %shuffle
+}