[PATCH] D58521: [DAGCombiner] allow truncation of binops after legalization if desirable

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: arsenm, jonpa, efriedma, uweigand, nhaehnle, craig.topper, RKSimon, andreadb.
Herald added subscribers: jsji, hiraditya, tpr, wdng, jvesely, nemanjai, mcrosier.
Herald added a project: LLVM.

This is an alternative to D58210 <https://reviews.llvm.org/D58210> that achieves similar results for SystemZ. I'm proposing to extend the general (trunc (binop X, Y)) transform by using the existing TLI hook isTypeDesirableForOp() if we are post-legalization. This allows eliminating the similar fold in distributeTruncateThroughAnd() that is oddly constrained by starting the pattern match only from shift/rotate.

About the test diffs:

1. AMDGPU: 'widen-smrd-loads' is an improvement and 'idot' diffs are regressions?
2. PowerPC: neutral
3. SystemZ: improvements or neutral
4. x86: mostly neutral, improvements with 'shld/shrd', and regressions for 'vector-sext'.

I did look at the x86 'vector-sext' regressions, and the seemingly unnecessary 'movzbl' are being inserted by an isel pattern because:

  // anyext. Define these to do an explicit zero-extend to
  // avoid partial-register updates.

So that conflicts with the x86 setting that says 8-bit ops are desirable. Ideally, we would defer partial-reg optimizations to a later pass (and I know we already do this for some cases, so maybe that just needs to be adjusted a bit).


https://reviews.llvm.org/D58521

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AMDGPU/idot8s.ll
  llvm/test/CodeGen/AMDGPU/idot8u.ll
  llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
  llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
  llvm/test/CodeGen/SystemZ/scalar-ctlz.ll
  llvm/test/CodeGen/X86/and-encoding.ll
  llvm/test/CodeGen/X86/avx512-mask-op.ll
  llvm/test/CodeGen/X86/bool-math.ll
  llvm/test/CodeGen/X86/clz.ll
  llvm/test/CodeGen/X86/fast-isel-cmp.ll
  llvm/test/CodeGen/X86/funnel-shift.ll
  llvm/test/CodeGen/X86/mul-constant-i8.ll
  llvm/test/CodeGen/X86/pr15267.ll
  llvm/test/CodeGen/X86/pr40539.ll
  llvm/test/CodeGen/X86/replace-load-and-with-bzhi.ll
  llvm/test/CodeGen/X86/shift-double-x86_64.ll
  llvm/test/CodeGen/X86/shift-double.ll
  llvm/test/CodeGen/X86/vector-sext-widen.ll
  llvm/test/CodeGen/X86/vector-sext.ll

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