[llvm] r354592 - AMDGPU/GlobalISel: Make phis legal
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 21 07:48:13 PST 2019
Author: arsenm
Date: Thu Feb 21 07:48:13 2019
New Revision: 354592
URL: http://llvm.org/viewvc/llvm-project?rev=354592&view=rev
Log:
AMDGPU/GlobalISel: Make phis legal
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=354592&r1=354591&r2=354592&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Thu Feb 21 07:48:13 2019
@@ -149,6 +149,19 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
setAction({G_BRCOND, S1}, Legal);
+ // TODO: All multiples of 32, vectors of pointers, all v2s16 pairs, more
+ // elements for v3s16
+ getActionDefinitionsBuilder(G_PHI)
+ .legalFor({S32, S64, V2S16, V4S16, S1, S128, S256})
+ .legalFor(AllS32Vectors)
+ .legalFor(AllS64Vectors)
+ .legalFor(AddrSpaces64)
+ .legalFor(AddrSpaces32)
+ .clampScalar(0, S32, S256)
+ .widenScalarToNextPow2(0, 32)
+ .legalIf(isPointer(0));
+
+
getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_UMULH, G_SMULH})
.legalFor({S32})
.clampScalar(0, S32, S32)
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir?rev=354592&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir Thu Feb 21 07:48:13 2019
@@ -0,0 +1,1109 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
+
+---
+name: test_phi_s32
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_s32
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY]](s32), %bb.0, [[ADD]](s32), %bb.1
+ ; CHECK: $vgpr0 = COPY [[PHI]](s32)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0, $vgpr1
+
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %4:_(s32) = G_ADD %0, %0
+ G_BR %bb.2
+
+ bb.2:
+ %5:_(s32) = G_PHI %0, %bb.0, %4, %bb.1
+ $vgpr0 = COPY %5
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: test_phi_v2s16
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_v2s16
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
+ ; CHECK: [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
+ ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT]], [[ANYEXT1]]
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+ ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
+ ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT2]], [[ANYEXT3]]
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(<2 x s16>) = G_PHI [[COPY]](<2 x s16>), %bb.0, [[BUILD_VECTOR]](<2 x s16>), %bb.1
+ ; CHECK: $vgpr0 = COPY [[PHI]](<2 x s16>)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0, $vgpr1
+
+ %0:_(<2 x s16>) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %5:_(<2 x s16>) = G_ADD %0, %0
+ G_BR %bb.2
+
+ bb.2:
+ %6:_(<2 x s16>) = G_PHI %0, %bb.0, %5, %bb.1
+ $vgpr0 = COPY %6
+ S_SETPC_B64 undef $sgpr30_sgpr31
+...
+---
+name: test_phi_v4s16
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_v4s16
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
+ ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
+ ; CHECK: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
+ ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s16)
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT]], [[ANYEXT1]]
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+ ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
+ ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s16)
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT2]], [[ANYEXT3]]
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
+ ; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
+ ; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s16)
+ ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT4]], [[ANYEXT5]]
+ ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD2]](s32)
+ ; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
+ ; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s16)
+ ; CHECK: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT6]], [[ANYEXT7]]
+ ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[ADD3]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16)
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(<4 x s16>) = G_PHI [[COPY]](<4 x s16>), %bb.0, [[BUILD_VECTOR]](<4 x s16>), %bb.1
+ ; CHECK: $vgpr0_vgpr1 = COPY [[PHI]](<4 x s16>)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0_vgpr1, $vgpr2
+
+ %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
+ %1:_(s32) = COPY $vgpr2
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %4:_(<4 x s16>) = G_ADD %0, %0
+ G_BR %bb.2
+
+ bb.2:
+ %5:_(<4 x s16>) = G_PHI %0, %bb.0, %4, %bb.1
+ $vgpr0_vgpr1 = COPY %5
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: test_phi_v2s32
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_v2s32
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+ ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[UV2]]
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UV3]]
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32)
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(<2 x s32>) = G_PHI [[COPY]](<2 x s32>), %bb.0, [[BUILD_VECTOR]](<2 x s32>), %bb.1
+ ; CHECK: $vgpr0_vgpr1 = COPY [[PHI]](<2 x s32>)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0_vgpr1, $vgpr2
+
+ %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
+ %1:_(s32) = COPY $vgpr2
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %4:_(<2 x s32>) = G_ADD %0, %0
+ G_BR %bb.2
+
+ bb.2:
+ %5:_(<2 x s32>) = G_PHI %0, %bb.0, %4, %bb.1
+ $vgpr0_vgpr1 = COPY %5
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: test_phi_v3s32
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_v3s32
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
+ ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
+ ; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[UV3]]
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UV4]]
+ ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[UV2]], [[UV5]]
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32), [[ADD2]](s32)
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(<3 x s32>) = G_PHI [[COPY]](<3 x s32>), %bb.0, [[BUILD_VECTOR]](<3 x s32>), %bb.1
+ ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[PHI]](<3 x s32>)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0_vgpr1_vgpr2, $vgpr3
+
+ %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
+ %1:_(s32) = COPY $vgpr3
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %4:_(<3 x s32>) = G_ADD %0, %0
+ G_BR %bb.2
+
+ bb.2:
+ %5:_(<3 x s32>) = G_PHI %0, %bb.0, %4, %bb.1
+ $vgpr0_vgpr1_vgpr2 = COPY %5
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: test_phi_v4s32
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_v4s32
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
+ ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+ ; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[UV4]]
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UV5]]
+ ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[UV2]], [[UV6]]
+ ; CHECK: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UV3]], [[UV7]]
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32), [[ADD2]](s32), [[ADD3]](s32)
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(<4 x s32>) = G_PHI [[COPY]](<4 x s32>), %bb.0, [[BUILD_VECTOR]](<4 x s32>), %bb.1
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[PHI]](<4 x s32>)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
+
+ %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(s32) = COPY $vgpr4
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %4:_(<4 x s32>) = G_ADD %0, %0
+ G_BR %bb.2
+
+ bb.2:
+ %5:_(<4 x s32>) = G_PHI %0, %bb.0, %4, %bb.1
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %5
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: test_phi_s64
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_s64
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; CHECK: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+ ; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV]], [[UV2]], [[C1]]
+ ; CHECK: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDE1]]
+ ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDE]](s32), [[UADDE2]](s32)
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[COPY]](s64), %bb.0, [[MV]](s64), %bb.1
+ ; CHECK: $vgpr0_vgpr1 = COPY [[PHI]](s64)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0_vgpr1, $vgpr2
+
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s32) = COPY $vgpr2
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %4:_(s64) = G_ADD %0, %0
+ G_BR %bb.2
+
+ bb.2:
+ %5:_(s64) = G_PHI %0, %bb.0, %4, %bb.1
+ $vgpr0_vgpr1 = COPY %5
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: test_phi_v2s64
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_v2s64
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
+ ; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
+ ; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
+ ; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
+ ; CHECK: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s1) = COPY [[C1]](s1)
+ ; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV4]], [[UV6]], [[COPY2]]
+ ; CHECK: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UV5]], [[UV7]], [[UADDE1]]
+ ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDE]](s32), [[UADDE2]](s32)
+ ; CHECK: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
+ ; CHECK: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
+ ; CHECK: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UV8]], [[UV10]], [[C1]]
+ ; CHECK: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UV9]], [[UV11]], [[UADDE5]]
+ ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDE4]](s32), [[UADDE6]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(<2 x s64>) = G_PHI [[COPY]](<2 x s64>), %bb.0, [[BUILD_VECTOR]](<2 x s64>), %bb.1
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[PHI]](<2 x s64>)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
+
+ %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(s32) = COPY $vgpr4
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %4:_(<2 x s64>) = G_ADD %0, %0
+ G_BR %bb.2
+
+ bb.2:
+ %5:_(<2 x s64>) = G_PHI %0, %bb.0, %4, %bb.1
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %5
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: test_phi_v3s64
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_v3s64
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8
+ ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s64>) = G_EXTRACT [[COPY]](<4 x s64>), 0
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s64>)
+ ; CHECK: [[UV3:%[0-9]+]]:_(s64), [[UV4:%[0-9]+]]:_(s64), [[UV5:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s64>)
+ ; CHECK: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
+ ; CHECK: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
+ ; CHECK: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s1) = COPY [[C1]](s1)
+ ; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV6]], [[UV8]], [[COPY2]]
+ ; CHECK: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UV7]], [[UV9]], [[UADDE1]]
+ ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDE]](s32), [[UADDE2]](s32)
+ ; CHECK: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
+ ; CHECK: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV4]](s64)
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s1) = COPY [[C1]](s1)
+ ; CHECK: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UV10]], [[UV12]], [[COPY3]]
+ ; CHECK: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UV11]], [[UV13]], [[UADDE5]]
+ ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDE4]](s32), [[UADDE6]](s32)
+ ; CHECK: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
+ ; CHECK: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV5]](s64)
+ ; CHECK: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UV14]], [[UV16]], [[C1]]
+ ; CHECK: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UV15]], [[UV17]], [[UADDE9]]
+ ; CHECK: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDE8]](s32), [[UADDE10]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64), [[MV2]](s64)
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(<3 x s64>) = G_PHI [[EXTRACT]](<3 x s64>), %bb.0, [[BUILD_VECTOR]](<3 x s64>), %bb.1
+ ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s64>) = G_IMPLICIT_DEF
+ ; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s64>) = G_INSERT [[DEF]], [[PHI]](<3 x s64>), 0
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INSERT]](<4 x s64>)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8
+
+ %0:_(<4 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ %1:_(s32) = COPY $vgpr8
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ %4:_(<3 x s64>) = G_EXTRACT %0, 0
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %5:_(<3 x s64>) = G_ADD %4, %4
+ G_BR %bb.2
+
+ bb.2:
+ %6:_(<3 x s64>) = G_PHI %4, %bb.0, %5, %bb.1
+ %7:_(<4 x s64>) = G_IMPLICIT_DEF
+ %8:_(<4 x s64>) = G_INSERT %7, %6, 0
+ $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %8
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: test_phi_p3
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_p3
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK: [[GEP:%[0-9]+]]:_(p3) = G_GEP [[COPY]], [[C1]](s32)
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(p3) = G_PHI [[COPY]](p3), %bb.0, [[GEP]](p3), %bb.1
+ ; CHECK: $vgpr0 = COPY [[PHI]](p3)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0, $vgpr1
+
+ %0:_(p3) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %4:_(s32) = G_CONSTANT i32 8
+ %5:_(p3) = G_GEP %0, %4
+ G_BR %bb.2
+
+ bb.2:
+ %6:_(p3) = G_PHI %0, %bb.0, %5, %bb.1
+ $vgpr0 = COPY %6
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: test_phi_p5
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_p5
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK: [[GEP:%[0-9]+]]:_(p5) = G_GEP [[COPY]], [[C1]](s32)
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(p5) = G_PHI [[COPY]](p5), %bb.0, [[GEP]](p5), %bb.1
+ ; CHECK: $vgpr0 = COPY [[PHI]](p5)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0, $vgpr1
+
+ %0:_(p5) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %4:_(s32) = G_CONSTANT i32 8
+ %5:_(p5) = G_GEP %0, %4
+ G_BR %bb.2
+
+ bb.2:
+ %6:_(p5) = G_PHI %0, %bb.0, %5, %bb.1
+ $vgpr0 = COPY %6
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: test_phi_p0
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_p0
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C1]](s64)
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(p0) = G_PHI [[COPY]](p0), %bb.0, [[GEP]](p0), %bb.1
+ ; CHECK: $vgpr0_vgpr1 = COPY [[PHI]](p0)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0_vgpr1, $vgpr2
+
+ %0:_(p0) = COPY $vgpr0_vgpr1
+ %1:_(s32) = COPY $vgpr2
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %4:_(s64) = G_CONSTANT i64 8
+ %5:_(p0) = G_GEP %0, %4
+ G_BR %bb.2
+
+ bb.2:
+ %6:_(p0) = G_PHI %0, %bb.0, %5, %bb.1
+ $vgpr0_vgpr1 = COPY %6
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: test_phi_p1
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_p1
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; CHECK: [[GEP:%[0-9]+]]:_(p1) = G_GEP [[COPY]], [[C1]](s64)
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(p1) = G_PHI [[COPY]](p1), %bb.0, [[GEP]](p1), %bb.1
+ ; CHECK: $vgpr0_vgpr1 = COPY [[PHI]](p1)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0_vgpr1, $vgpr2
+
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = COPY $vgpr2
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %4:_(s64) = G_CONSTANT i64 8
+ %5:_(p1) = G_GEP %0, %4
+ G_BR %bb.2
+
+ bb.2:
+ %6:_(p1) = G_PHI %0, %bb.0, %5, %bb.1
+ $vgpr0_vgpr1 = COPY %6
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: test_phi_p4
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_p4
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
+ ; CHECK: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; CHECK: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64)
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(p4) = G_PHI [[COPY]](p4), %bb.0, [[GEP]](p4), %bb.1
+ ; CHECK: $vgpr0_vgpr1 = COPY [[PHI]](p4)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0_vgpr1, $vgpr2
+
+ %0:_(p4) = COPY $vgpr0_vgpr1
+ %1:_(s32) = COPY $vgpr2
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %4:_(s64) = G_CONSTANT i64 8
+ %5:_(p4) = G_GEP %0, %4
+ G_BR %bb.2
+
+ bb.2:
+ %6:_(p4) = G_PHI %0, %bb.0, %5, %bb.1
+ $vgpr0_vgpr1 = COPY %6
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: test_phi_p9999
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_p9999
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
+ ; CHECK: [[COPY:%[0-9]+]]:_(p9999) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[DEF:%[0-9]+]]:_(p9999) = G_IMPLICIT_DEF
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(p9999) = G_PHI [[COPY]](p9999), %bb.0, [[DEF]](p9999), %bb.1
+ ; CHECK: $vgpr0_vgpr1 = COPY [[PHI]](p9999)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0_vgpr1, $vgpr2
+
+ %0:_(p9999) = COPY $vgpr0_vgpr1
+ %1:_(s32) = COPY $vgpr2
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %4:_(p9999) = G_IMPLICIT_DEF
+ G_BR %bb.2
+
+ bb.2:
+ %5:_(p9999) = G_PHI %0, %bb.0, %4, %bb.1
+ $vgpr0_vgpr1 = COPY %5
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: test_phi_s1
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_s1
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(s1) = G_PHI [[TRUNC]](s1), %bb.0, [[DEF]](s1), %bb.1
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[PHI]](s1)
+ ; CHECK: $vgpr0 = COPY [[ZEXT]](s32)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0, $vgpr1
+
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ %4:_(s1) = G_TRUNC %1
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %5:_(s1) = G_IMPLICIT_DEF
+ G_BR %bb.2
+
+ bb.2:
+ %6:_(s1) = G_PHI %4, %bb.0, %5, %bb.1
+ %7:_(s32) = G_ZEXT %6
+ $vgpr0 = COPY %7
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: test_phi_s7
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_s7
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY2]](s32), %bb.0, [[COPY3]](s32), %bb.1
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[PHI]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CHECK: $vgpr0 = COPY [[AND]](s32)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0, $vgpr1
+
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ %4:_(s7) = G_TRUNC %1
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %5:_(s7) = G_IMPLICIT_DEF
+ G_BR %bb.2
+
+ bb.2:
+ %6:_(s7) = G_PHI %4, %bb.0, %5, %bb.1
+ %7:_(s32) = G_ZEXT %6
+ $vgpr0 = COPY %7
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: test_phi_s8
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_s8
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY2]](s32), %bb.0, [[COPY3]](s32), %bb.1
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[PHI]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CHECK: $vgpr0 = COPY [[AND]](s32)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0, $vgpr1
+
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ %4:_(s8) = G_TRUNC %1
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %5:_(s8) = G_IMPLICIT_DEF
+ G_BR %bb.2
+
+ bb.2:
+ %6:_(s8) = G_PHI %4, %bb.0, %5, %bb.1
+ %7:_(s32) = G_ZEXT %6
+ $vgpr0 = COPY %7
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: test_phi_s16
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_s16
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY2]](s32), %bb.0, [[COPY3]](s32), %bb.1
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[PHI]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CHECK: $vgpr0 = COPY [[AND]](s32)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0, $vgpr1
+
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ %4:_(s16) = G_TRUNC %1
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %5:_(s16) = G_IMPLICIT_DEF
+ G_BR %bb.2
+
+ bb.2:
+ %6:_(s16) = G_PHI %4, %bb.0, %5, %bb.1
+ %7:_(s32) = G_ZEXT %6
+ $vgpr0 = COPY %7
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: test_phi_s128
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_s128
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
+ ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr4
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s128)
+ ; CHECK: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+ ; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV]], [[UV4]], [[C1]]
+ ; CHECK: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV5]], [[UADDE1]]
+ ; CHECK: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UV2]], [[UV6]], [[UADDE3]]
+ ; CHECK: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UV3]], [[UV7]], [[UADDE5]]
+ ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[UADDE]](s32), [[UADDE2]](s32), [[UADDE4]](s32), [[UADDE6]](s32)
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(s128) = G_PHI [[COPY]](s128), %bb.0, [[MV]](s128), %bb.1
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[PHI]](s128)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
+
+ %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+ %1:_(s32) = COPY $vgpr4
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %4:_(s128) = G_ADD %0, %0
+ G_BR %bb.2
+
+ bb.2:
+ %5:_(s128) = G_PHI %0, %bb.0, %4, %bb.1
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %5
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: test_phi_s256
+tracksRegLiveness: true
+
+body: |
+ ; CHECK-LABEL: name: test_phi_s256
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8
+ ; CHECK: [[COPY:%[0-9]+]]:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
+ ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s256)
+ ; CHECK: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s256)
+ ; CHECK: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+ ; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV]], [[UV8]], [[C1]]
+ ; CHECK: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV9]], [[UADDE1]]
+ ; CHECK: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UV2]], [[UV10]], [[UADDE3]]
+ ; CHECK: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UV3]], [[UV11]], [[UADDE5]]
+ ; CHECK: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UV4]], [[UV12]], [[UADDE7]]
+ ; CHECK: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UV5]], [[UV13]], [[UADDE9]]
+ ; CHECK: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[UV6]], [[UV14]], [[UADDE11]]
+ ; CHECK: [[UADDE14:%[0-9]+]]:_(s32), [[UADDE15:%[0-9]+]]:_(s1) = G_UADDE [[UV7]], [[UV15]], [[UADDE13]]
+ ; CHECK: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UADDE]](s32), [[UADDE2]](s32), [[UADDE4]](s32), [[UADDE6]](s32), [[UADDE8]](s32), [[UADDE10]](s32), [[UADDE12]](s32), [[UADDE14]](s32)
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(s256) = G_PHI [[COPY]](s256), %bb.0, [[MV]](s256), %bb.1
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[PHI]](s256)
+ ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8
+
+ %0:_(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+ %1:_(s32) = COPY $vgpr8
+ %2:_(s32) = G_CONSTANT i32 0
+ %3:_(s1) = G_ICMP intpred(eq), %1, %2
+ G_BRCOND %3, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %4:_(s256) = G_ADD %0, %0
+ G_BR %bb.2
+
+ bb.2:
+ %5:_(s256) = G_PHI %0, %bb.0, %4, %bb.1
+ $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %5
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
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