[PATCH] D58460: [AArch64] Optimize floating point materialization

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:5394
+  unsigned LZ = countLeadingZeros((uint64_t)Val);
+  return (RegSize - LZ + 15) / 16;
+}
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Please don't copy-paste code.  And this is a very inaccurate approximation for the logic in AArch64ExpandPseudo::expandMOVImm.


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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:5400
+// pressure. The timings are still the same if you consider movw+movk+fmov
+// vs. adrp+ldr (it's one instruction longer, but the movw+movk is fused).
 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
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Not sure this comment should be here; should be next to the code that actually makes this decision.


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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:5424
+    // at maximum of 2 moves to match and adrl+ldr cost.
+    IsLegal = getIntImmCost(ImmInt.getZExtValue(), VT.getSizeInBits()) <= 2;
 
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Does it matter whether we're optimizing for size?


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58460/new/

https://reviews.llvm.org/D58460