[PATCH] D58466: [AArch64][GlobalISel] Implement partial support for G_SHUFFLE_VECTOR
Amara Emerson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 20 11:31:42 PST 2019
aemerson created this revision.
aemerson added a reviewer: paquette.
aemerson added a project: LLVM.
Herald added subscribers: Petar.Avramovic, hiraditya, kristof.beyls, javed.absar, rovka.
aemerson updated this revision to Diff 187633.
aemerson added a comment.
Remove commented out line.
This change makes some basic type combinations for G_SHUFFLE_VECTOR legal, and implements them with a very pessimistic TBL2 instruction in the selector.
For TBL2, support is also needed to generate constant pool entries and load from them in order to materialize the mask register.
Currently supports <2 x s64> and <4 x s32> result types.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D58466
Files:
llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir
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