[llvm] r354427 - [PowerPC] exploit P9 instruction maddld.
Chen Zheng via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 19 18:30:06 PST 2019
Author: shchenz
Date: Tue Feb 19 18:30:06 2019
New Revision: 354427
URL: http://llvm.org/viewvc/llvm-project?rev=354427&view=rev
Log:
[PowerPC] exploit P9 instruction maddld.
Differential Revision: https://reviews.llvm.org/D58364
Added:
llvm/trunk/test/CodeGen/PowerPC/maddld.ll
Modified:
llvm/trunk/lib/Target/PowerPC/P9InstrResources.td
llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
Modified: llvm/trunk/lib/Target/PowerPC/P9InstrResources.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/P9InstrResources.td?rev=354427&r1=354426&r2=354427&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/P9InstrResources.td (original)
+++ llvm/trunk/lib/Target/PowerPC/P9InstrResources.td Tue Feb 19 18:30:06 2019
@@ -399,7 +399,7 @@ def : InstRW<[P9_DPE_7C, P9_DPO_7C, IP_E
// dispatch units for the superslice.
def : InstRW<[P9_DP_5C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
(instrs
- (instregex "MADD(HD|HDU|LD)$"),
+ (instregex "MADD(HD|HDU|LD|LD8)$"),
(instregex "MUL(HD|HW|LD|LI|LI8|LW)(U)?$")
)>;
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=354427&r1=354426&r2=354427&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Tue Feb 19 18:30:06 2019
@@ -772,13 +772,21 @@ def DIVDE : XOForm_1<31, 425, 0, (outs g
let Predicates = [IsISA3_0] in {
def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
"maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
-def MADDHDU : VAForm_1a<49, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
+def MADDHDU : VAForm_1a<49,
+ (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
"maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
-def MADDLD : VAForm_1a<51, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
- "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
+def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC),
+ "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD,
+ [(set i32:$RT, (add (mul i32:$RA, i32:$RB), i32:$RC))]>,
+ isPPC64;
def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA),
"setb $RT, $BFA", IIC_IntGeneral>, isPPC64;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
+ def MADDLD8 : VAForm_1a<51,
+ (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
+ "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD,
+ [(set i64:$RT, (add (mul i64:$RA, i64:$RB), i64:$RC))]>,
+ isPPC64;
def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA),
"setb $RT, $BFA", IIC_IntGeneral>, isPPC64;
}
Added: llvm/trunk/test/CodeGen/PowerPC/maddld.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/maddld.ll?rev=354427&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/maddld.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/maddld.ll Tue Feb 19 18:30:06 2019
@@ -0,0 +1,115 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-P9
+; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-P8
+
+define signext i64 @maddld64(i64 signext %a, i64 signext %b) {
+; CHECK-P9-LABEL: maddld64:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: maddld 3, 4, 3, 3
+; CHECK-P9-NEXT: blr
+;
+; CHECK-P8-LABEL: maddld64:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: mulld 4, 4, 3
+; CHECK-P8-NEXT: add 3, 4, 3
+; CHECK-P8-NEXT: blr
+entry:
+ %mul = mul i64 %b, %a
+ %add = add i64 %mul, %a
+ ret i64 %add
+}
+
+define signext i32 @maddld32(i32 signext %a, i32 signext %b) {
+; CHECK-P9-LABEL: maddld32:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: maddld 3, 4, 3, 3
+; CHECK-P9-NEXT: extsw 3, 3
+; CHECK-P9-NEXT: blr
+;
+; CHECK-P8-LABEL: maddld32:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: mullw 4, 4, 3
+; CHECK-P8-NEXT: add 3, 4, 3
+; CHECK-P8-NEXT: extsw 3, 3
+; CHECK-P8-NEXT: blr
+entry:
+ %mul = mul i32 %b, %a
+ %add = add i32 %mul, %a
+ ret i32 %add
+}
+
+define signext i16 @maddld16(i16 signext %a, i16 signext %b, i16 signext %c) {
+; CHECK-P9-LABEL: maddld16:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: maddld 3, 4, 3, 5
+; CHECK-P9-NEXT: extsh 3, 3
+; CHECK-P9-NEXT: blr
+;
+; CHECK-P8-LABEL: maddld16:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: mullw 3, 4, 3
+; CHECK-P8-NEXT: add 3, 3, 5
+; CHECK-P8-NEXT: extsh 3, 3
+; CHECK-P8-NEXT: blr
+entry:
+ %mul = mul i16 %b, %a
+ %add = add i16 %mul, %c
+ ret i16 %add
+}
+
+define zeroext i32 @maddld32zeroext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P9-LABEL: maddld32zeroext:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: maddld 3, 4, 3, 3
+; CHECK-P9-NEXT: clrldi 3, 3, 32
+; CHECK-P9-NEXT: blr
+;
+; CHECK-P8-LABEL: maddld32zeroext:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: mullw 4, 4, 3
+; CHECK-P8-NEXT: add 3, 4, 3
+; CHECK-P8-NEXT: clrldi 3, 3, 32
+; CHECK-P8-NEXT: blr
+entry:
+ %mul = mul i32 %b, %a
+ %add = add i32 %mul, %a
+ ret i32 %add
+}
+
+define signext i32 @maddld32nsw(i32 signext %a, i32 signext %b) {
+; CHECK-P9-LABEL: maddld32nsw:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: maddld 3, 4, 3, 3
+; CHECK-P9-NEXT: extsw 3, 3
+; CHECK-P9-NEXT: blr
+;
+; CHECK-P8-LABEL: maddld32nsw:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: mullw 4, 4, 3
+; CHECK-P8-NEXT: add 3, 4, 3
+; CHECK-P8-NEXT: extsw 3, 3
+; CHECK-P8-NEXT: blr
+entry:
+ %mul = mul nsw i32 %b, %a
+ %add = add nsw i32 %mul, %a
+ ret i32 %add
+}
+
+define zeroext i32 @maddld32nuw(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P9-LABEL: maddld32nuw:
+; CHECK-P9: # %bb.0: # %entry
+; CHECK-P9-NEXT: maddld 3, 4, 3, 3
+; CHECK-P9-NEXT: clrldi 3, 3, 32
+; CHECK-P9-NEXT: blr
+;
+; CHECK-P8-LABEL: maddld32nuw:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: mullw 4, 4, 3
+; CHECK-P8-NEXT: add 3, 4, 3
+; CHECK-P8-NEXT: clrldi 3, 3, 32
+; CHECK-P8-NEXT: blr
+entry:
+ %mul = mul nuw i32 %b, %a
+ %add = add nuw i32 %mul, %a
+ ret i32 %add
+}
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