[PATCH] D58281: [ARM] Add some more missing T1 opcodes for the peephole optimisier

[Eli Friedman via Phabricator via llvm-commits]

efriedma accepted this revision.
efriedma added a comment.
This revision is now accepted and ready to land.

LGTM



================
Comment at: lib/Target/ARM/ARMBaseInstrInfo.cpp:2830
     --I;
-    bool CanReorder = true;
-    const bool HasStmts = I != E;
-    for (; I != E; --I) {
-      if (I->getOpcode() != ARM::tMOVi8) {
-        CanReorder = false;
-        break;
+    if (I != E && !MI->readsRegister(ARM::CPSR, TRI)) {
+      bool CanReorder = true;
----------------
This change is necessary to prevent illegal reordering involving ADC/SBC, I guess?  And this is covered by the test test_adc_mov in peephole-mi.mir?  Maybe worth mentioning in the commit message.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58281/new/

https://reviews.llvm.org/D58281