[PATCH] D58363: [X86] Bugfix for nullptr check by klocwork

[Xiang Zhang via Phabricator via llvm-commits]

xiangzhangllvm added a comment.

Ok , I'll update it like this:

1 diff --git a/lib/Target/X86/X86InstructionSelector.cpp b/lib/Target/X86/X86InstructionSelector.cpp

  2 index c3c41fe..92de59b 100644
  3 --- a/lib/Target/X86/X86InstructionSelector.cpp
  4 +++ b/lib/Target/X86/X86InstructionSelector.cpp
  5 @@ -1600,11 +1600,8 @@ bool X86InstructionSelector::selectDivRem(MachineInstr &I,
  6    assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) &&
  7           "Arguments and return value types must match");
  8
  9 -  const RegisterBank *PtrRegRB = RBI.getRegBank(DstReg, MRI, TRI);

10 -  if (!PtrRegRB)
 11 -    return false;
 12 -  const RegisterBank &RegRB = *PtrRegRB;
 13 -  if (RegRB.getID() != X86::GPRRegBankID)
 14 +  const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI);
 15 +  if (!RegRB && RegRB->getID() != X86::GPRRegBankID)
 16      return false;
17
 18    const static unsigned NumTypes = 4; // i8, i16, i32, i64
 19 @@ -1702,7 +1699,7 @@ bool X86InstructionSelector::selectDivRem(MachineInstr &I,
 20    const DivRemEntry &TypeEntry = *OpEntryIt;
 21    const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex];
22
 23 -  const TargetRegisterClass *RegRC = getRegClass(RegTy, RegRB);
 24 +  const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB);
 25    if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) ||
 26        !RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) ||
 27        !RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) {


Repository:
  rL LLVM

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  https://reviews.llvm.org/D58363/new/

https://reviews.llvm.org/D58363