[llvm] r354261 - [MCA] Slightly refactor method writeStartEvent in WriteState and ReadState. NFCI
Andrea Di Biagio via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 18 03:27:11 PST 2019
Author: adibiagio
Date: Mon Feb 18 03:27:11 2019
New Revision: 354261
URL: http://llvm.org/viewvc/llvm-project?rev=354261&view=rev
Log:
[MCA] Slightly refactor method writeStartEvent in WriteState and ReadState. NFCI
This is another change in preparation for PR37494.
No functional change intended.
Modified:
llvm/trunk/include/llvm/MCA/Instruction.h
llvm/trunk/lib/MCA/HardwareUnits/RegisterFile.cpp
llvm/trunk/lib/MCA/HardwareUnits/Scheduler.cpp
llvm/trunk/lib/MCA/Instruction.cpp
Modified: llvm/trunk/include/llvm/MCA/Instruction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MCA/Instruction.h?rev=354261&r1=354260&r2=354261&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MCA/Instruction.h (original)
+++ llvm/trunk/include/llvm/MCA/Instruction.h Mon Feb 18 03:27:11 2019
@@ -150,9 +150,17 @@ public:
unsigned getRegisterID() const { return RegisterID; }
unsigned getRegisterFileID() const { return PRFID; }
unsigned getLatency() const { return WD->Latency; }
+ const WriteState *getDependentWrite() const { return DependentWrite; }
- void addUser(ReadState *Use, int ReadAdvance);
- void addUser(WriteState *Use);
+ // This method adds Use to the set of data dependent reads. IID is the
+ // instruction identifier associated with this write. ReadAdvance is the
+ // number of cycles to subtract from the latency of this data dependency.
+ // Use is in a RAW dependency with this write.
+ void addUser(unsigned IID, ReadState *Use, int ReadAdvance);
+
+ // Use is a younger register write that is in a false dependency with this
+ // write. IID is the instruction identifier associated with this write.
+ void addUser(unsigned IID, WriteState *Use);
unsigned getDependentWriteCyclesLeft() const {
return DependentWriteCyclesLeft;
@@ -170,7 +178,7 @@ public:
bool isEliminated() const { return IsEliminated; }
bool isReady() const {
- if (getDependentWrite())
+ if (DependentWrite)
return false;
unsigned CyclesLeft = getDependentWriteCyclesLeft();
return !CyclesLeft || CyclesLeft < getLatency();
@@ -180,9 +188,8 @@ public:
return CyclesLeft != UNKNOWN_CYCLES && CyclesLeft <= 0;
}
- const WriteState *getDependentWrite() const { return DependentWrite; }
- void setDependentWrite(WriteState *Other) { DependentWrite = Other; }
- void writeStartEvent(unsigned Cycles) {
+ void setDependentWrite(const WriteState *Other) { DependentWrite = Other; }
+ void writeStartEvent(unsigned IID, unsigned RegID, unsigned Cycles) {
DependentWriteCyclesLeft = Cycles;
DependentWrite = nullptr;
}
@@ -198,7 +205,7 @@ public:
// On every cycle, update CyclesLeft and notify dependent users.
void cycleEvent();
- void onInstructionIssued();
+ void onInstructionIssued(unsigned IID);
#ifndef NDEBUG
void dump() const;
@@ -255,7 +262,7 @@ public:
void setIndependentFromDef() { IndependentFromDef = true; }
void cycleEvent();
- void writeStartEvent(unsigned Cycles);
+ void writeStartEvent(unsigned IID, unsigned RegID, unsigned Cycles);
void setDependentWrites(unsigned Writes) {
DependentWrites = Writes;
IsReady = !Writes;
@@ -454,8 +461,8 @@ public:
void dispatch(unsigned RCUTokenID);
// Instruction issued. Transition to the IS_EXECUTING state, and update
- // all the definitions.
- void execute();
+ // all the register definitions.
+ void execute(unsigned IID);
// Force a transition from the IS_DISPATCHED state to the IS_READY or
// IS_PENDING state. State transitions normally occur either at the beginning
@@ -556,7 +563,7 @@ public:
return !WS || WS->isExecuted();
}
- bool isValid() const { return Data.first != INVALID_IID && Data.second; }
+ bool isValid() const { return Data.second && Data.first != INVALID_IID; }
bool operator==(const WriteRef &Other) const { return Data == Other.Data; }
#ifndef NDEBUG
Modified: llvm/trunk/lib/MCA/HardwareUnits/RegisterFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MCA/HardwareUnits/RegisterFile.cpp?rev=354261&r1=354260&r2=354261&view=diff
==============================================================================
--- llvm/trunk/lib/MCA/HardwareUnits/RegisterFile.cpp (original)
+++ llvm/trunk/lib/MCA/HardwareUnits/RegisterFile.cpp Mon Feb 18 03:27:11 2019
@@ -188,7 +188,7 @@ void RegisterFile::addRegisterWrite(Writ
if (OtherWS && (OtherWrite.getSourceIndex() != Write.getSourceIndex())) {
// This partial write has a false dependency on RenameAs.
assert(!IsEliminated && "Unexpected partial update!");
- OtherWS->addUser(&WS);
+ OtherWS->addUser(OtherWrite.getSourceIndex(), &WS);
}
}
}
@@ -425,7 +425,7 @@ void RegisterFile::addRegisterRead(ReadS
WriteState &WS = *WR.getWriteState();
unsigned WriteResID = WS.getWriteResourceID();
int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID);
- WS.addUser(&RS, ReadAdvance);
+ WS.addUser(WR.getSourceIndex(), &RS, ReadAdvance);
}
}
Modified: llvm/trunk/lib/MCA/HardwareUnits/Scheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MCA/HardwareUnits/Scheduler.cpp?rev=354261&r1=354260&r2=354261&view=diff
==============================================================================
--- llvm/trunk/lib/MCA/HardwareUnits/Scheduler.cpp (original)
+++ llvm/trunk/lib/MCA/HardwareUnits/Scheduler.cpp Mon Feb 18 03:27:11 2019
@@ -74,7 +74,7 @@ void Scheduler::issueInstructionImpl(
// Notify the instruction that it started executing.
// This updates the internal state of each write.
- IS->execute();
+ IS->execute(IR.getSourceIndex());
if (IS->isExecuting())
IssuedSet.emplace_back(IR);
Modified: llvm/trunk/lib/MCA/Instruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MCA/Instruction.cpp?rev=354261&r1=354260&r2=354261&view=diff
==============================================================================
--- llvm/trunk/lib/MCA/Instruction.cpp (original)
+++ llvm/trunk/lib/MCA/Instruction.cpp Mon Feb 18 03:27:11 2019
@@ -18,7 +18,7 @@
namespace llvm {
namespace mca {
-void ReadState::writeStartEvent(unsigned Cycles) {
+void ReadState::writeStartEvent(unsigned IID, unsigned RegID, unsigned Cycles) {
assert(DependentWrites);
assert(CyclesLeft == UNKNOWN_CYCLES);
@@ -36,7 +36,7 @@ void ReadState::writeStartEvent(unsigned
}
}
-void WriteState::onInstructionIssued() {
+void WriteState::onInstructionIssued(unsigned IID) {
assert(CyclesLeft == UNKNOWN_CYCLES);
// Update the number of cycles left based on the WriteDescriptor info.
CyclesLeft = getLatency();
@@ -46,30 +46,30 @@ void WriteState::onInstructionIssued() {
for (const std::pair<ReadState *, int> &User : Users) {
ReadState *RS = User.first;
unsigned ReadCycles = std::max(0, CyclesLeft - User.second);
- RS->writeStartEvent(ReadCycles);
+ RS->writeStartEvent(IID, RegisterID, ReadCycles);
}
// Notify any writes that are in a false dependency with this write.
if (PartialWrite)
- PartialWrite->writeStartEvent(CyclesLeft);
+ PartialWrite->writeStartEvent(IID, RegisterID, CyclesLeft);
}
-void WriteState::addUser(ReadState *User, int ReadAdvance) {
+void WriteState::addUser(unsigned IID, ReadState *User, int ReadAdvance) {
// If CyclesLeft is different than -1, then we don't need to
// update the list of users. We can just notify the user with
// the actual number of cycles left (which may be zero).
if (CyclesLeft != UNKNOWN_CYCLES) {
unsigned ReadCycles = std::max(0, CyclesLeft - ReadAdvance);
- User->writeStartEvent(ReadCycles);
+ User->writeStartEvent(IID, RegisterID, ReadCycles);
return;
}
Users.emplace_back(User, ReadAdvance);
}
-void WriteState::addUser(WriteState *User) {
+void WriteState::addUser(unsigned IID, WriteState *User) {
if (CyclesLeft != UNKNOWN_CYCLES) {
- User->writeStartEvent(std::max(0, CyclesLeft));
+ User->writeStartEvent(IID, RegisterID, std::max(0, CyclesLeft));
return;
}
@@ -131,7 +131,7 @@ void Instruction::dispatch(unsigned RCUT
updatePending();
}
-void Instruction::execute() {
+void Instruction::execute(unsigned IID) {
assert(Stage == IS_READY);
Stage = IS_EXECUTING;
@@ -139,7 +139,7 @@ void Instruction::execute() {
CyclesLeft = getLatency();
for (WriteState &WS : getDefs())
- WS.onInstructionIssued();
+ WS.onInstructionIssued(IID);
// Transition to the "executed" stage if this is a zero-latency instruction.
if (!CyclesLeft)
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